I am implementing a simple counter which is counting the number of time push buttons are pressed. I wrote the following code:
module lock(
anodes,cathodes,leds,
sw,btns,clk );
//input declarations
input[7:0] sw;
input[3:0]btns;
input clk;
always #(curbtns)
begin
if( prevbtns!=0 && curbtns==0)
begin
counter_next = counter + 5'b00001;
end
else
counter_next = counter;
prevbtns = curbtns;
end
always #(btns or sw)
begin
case(btns)
4'b0001:curbtns=4'b0001;
4'b0010:curbtns=4'b0010;
4'b0100:curbtns=4'b0100;
4'b1000:curbtns=4'b1000;
4'b0000:curbtns=4'b0000;
default:curbtns = prevbtns;
endcase
end
always #(posedge clk)
begin
counter <=counter_next;
create_slow_clock(clk,slow_clock);
end
endmodule
When I simulate the above code in icraus verilog it seems to be working but on actual FPGA my counter is not changing. Is there any problem in the logic of incrementing the variable.
Updated code(Working)
always #(curbtns or prevbtns or counter)
begin
if( prevbtns!=0 && curbtns==0)
begin
counter_next = counter + 5'b00001;
end
else
counter_next = counter;
end
always #(posedge clk)
begin
counter <=counter_next;
prevbtns <=curbtns;
create_slow_clock(clk,slow_clock);
end
You look to be missing some signals in your sensitivity lists for the combinational always blocks.
For your code to be properly synthesizable, a combinational block must be sensitive to every input signal.
The first always block always #(curbtns) needs to be sensitive to prevbtns, curbtns, and counter.
The second block always #(btns or sw) also needs to be sensitive to prevbtns (I don't see sw used in this block anyway, should get rid of it).
I recommend changing both blocks to always #*, so that the lists may be automatically inferred, and it's not a fragile point of breakage if you change the logic and forget to change the list.
Related
How to fix multiple driver , default value and combinational loop problems in the code below?
always #(posedge clk)
myregister <= #1 myregisterNxt;
always #* begin
if(reset)
myregisterNxt = myregisterNxt +1;
else if(flag == 1)
myregister = myregister +2;
end
right there are at least 3 issues in your code:
you are driving myregister within 2 different always blocks. Synthesis will find multiple drivers there. Simulation results will be unpredictable. The rule: you must drive a signal within a single always block.
you ave a zero-delay loop over myregisterNxt = myregisterNxt +1. Since you are using a no-flop there, it is a real loop in simulation and in hardware. You need to break such loops with flops
#1 delay is not synthesizable and it is not needed here at all.
You have not described what you were trying to build and it is difficult to figure it out from our code sample. In general, reset is used to set up initial values. So, something like the following could be a template for you.
always #(posedge clk) begin
if (reset)
myregister <= 0;
else
myregister <= myregister + increment;
end
always #* begin
if (flag == 1)
increment = 1;
else
increment = 2;
end
the flop with posedge clk and nonblocking assignments will not be in a loop.
This is something that I think should be doable, but I am failing at how to do it in the HDL world. Currently I have a design I inherited that is summing a multidimensional array, but we have to pre-write the addition block because one of the dimensions is a synthesize-time option, and we cater the addition to that.
If I have something like reg tap_out[src][dst][tap], where src and dst is set to 4 and tap can be between 0 and 15 (16 possibilities), I want to be able to assign output[dst] be the sum of all the tap_out for that particular dst.
Right now our summation block takes all the combinations of tap_out for each src and tap and sums them in pairs for each dst:
tap_out[0][dst][0]
tap_out[1][dst][0]
tap_out[2][dst][0]
tap_out[3][dst][0]
tap_out[0][dst][1]
....
tap_out[3][dst][15]
Is there a way to do this better in Verilog? In C I would use some for-loops, but that doesn't seem possible here.
for-loops work perfectly fine in this situation
integer src_idx, tap_idx;
always #* begin
sum = 0;
for (scr_idx=0; src_idx<4; src_idx=scr_idx+1) begin
for (tap_idx=0; tap_idx<16; tap_idx=tap_idx+1) begin
sum = sum + tap_out[src_idx][dst][tap_idx];
end
end
end
It does unroll into a large combinational logic during synthesis and the results should be the same adding up the bits line by line.
Propagation delay from a large summing logic could have a timing issue. A good synthesizer should find the optimum timing/area when told the clocking constraint. If logic is too complex for the synthesizer, then add your own partial sum logic that can run in parallel
reg [`WIDHT-1:0] /*keep*/ partial_sum [3:0]; // tell synthesis to preserve these nets
integer src_idx, tap_idx;
always #* begin
sum = 0;
for (scr_idx=0; src_idx<4; src_idx=scr_idx+1) begin
partial_sum[scr_idx] = 0;
// partial sums are independent of each other so the can run in parallel
for (tap_idx=0; tap_idx<16; tap_idx=tap_idx+1) begin
partial_sum[scr_idx] = partial_sum[scr_idx] + tap_out[src_idx][dst][tap_idx];
end
sum = sum + partial_sum[scr_idx]; // sum the partial sums
end
end
If timing is still an issue, then you have must treat the logic as multi-cycle and sample the value some clock cycles after the input changed.
In RTL (the level of abstraction you are likely modelling with your HDL), you have to balance parallelism with time. By doing things in parallel, you save time (typically) but the logic takes up a lot of space. Conversely, you can make the adds completely serial (do one add at one time) and store the results in a register (it sounds like you want to accumulate the total sum, so I will explain that).
It sounds like the fully parallel is not practical for your uses (if it is and you want to rewrite it, look up generate statements). So, you'll need to create a small FSM and accumulate the sums into a register. Here's a basic example, which sums an array of 16-bit numbers (assume they are set somewhere else):
reg [15:0] arr[0:9]; // numbers
reg [31:0] result; // accumulated sum
reg load_result; // load signal for register containing result
reg clk, rst_L; // These are the clock and reset signals (reset asserted low)
/* This is a register for storing the result */
always #(posedge clk, negedge rst_L) begin
if (~rst_L) begin
result <= 32'd0;
end
else begin
if (load_result) begin
result <= next_result;
end
end
end
/* A counter for knowing which element of the array we are adding
reg [3:0] counter, next_counter;
reg load_counter;
always #(posedge clk, negedge rst_L) begin
if (~rst_L) begin
counter <= 4'd0;
end
else begin
if (load_counter) begin
counter <= counter + 4'd1;
end
end
end
/* Perform the addition */
assign next_result = result + arr[counter];
/* Define the state machine states and state variable */
localparam IDLE = 2'd0;
localparam ADDING = 2'd1;
localparam DONE = 2'd2;
reg [1:0] state, next_state;
/* A register for holding the current state */
always #(posedge clk, negedge rst_L) begin
if (~rst_L) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
/* The next state and output logic, this will control the addition */
always #(*) begin
/* Defaults */
next_state = IDLE;
load_result = 1'b0;
load_counter = 1'b0;
case (state)
IDLE: begin
next_state = ADDING; // Start adding now (right away)
end
ADDING: begin
load_result = 1'b1; // Load in the result
if (counter == 3'd9) begin // If we're on the last element, stop incrementing counter, we are done
load_counter = 1'b0;
next_state = DONE;
end
else begin // Otherwise, keep adding
load_counter = 1'b1;
next_state = ADDING;
end
end
DONE: begin // finished adding, result is in result!
next_state = DONE;
end
endcase
end
There are lots of resources on the web explaining FSMs if you are having trouble with the concept, but they can be used to implement your basic C-style for loop.
I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2 and learning the ins and outs.
I am trying to make a counter which is turned on and off by a switch.
So far the counter counts and resets based on a key press.
This is my error:
Error (10119): Verilog HDL Loop Statement error at my_first_counter_enable.v(19): loop with non-constant loop condition must terminate within 250 iterations
I understand I am being asked to provide a loop variable, but even doing so I get an error.
This is my code:
module my_first_counter_enable(SW,CLOCK_50,LEDR,KEY);
input CLOCK_50;
input [17:0] SW;
input KEY;
output [17:0] LEDR;
reg [32:0] count;
wire reset_n;
wire enable;
assign reset_n = KEY;
assign enable = SW[0];
assign LEDR = count[27:24];
always# (posedge CLOCK_50 or negedge reset_n) begin
while(enable) begin
if(!reset_n)
count = 0;
else
count = count + 1;
end
end
endmodule
I hope someone can point out my error in my loop and allow me to continue.
Thank you!
I don't think you want to use a while loop there. How about:
always# (posedge CLOCK_50 or negedge reset_n) begin
if(!reset_n)
count <= 0;
else if (enable)
count <= count + 1;
end
I also added non-blocking assignments <=, which are more appropriate for synchronous logic.
The block will trigger every time there is a positive edge of the clock. Where you had a while loop does not mean anything in hardware, it would still need a clock to drive the flip flops.
While loops can be used in testbeches to drive stimulus
integer x;
initial begin
x = 0;
while (x<1000) begin
data_in = 2**x ; //or stimulus read from file etc ...
x=x+1;
end
end
I find for loops or repeat to be of more use though:
integer x;
initial begin
for (x=0; x<1000; x=x+1) begin
data_in = 2**x ; //or stimulus read from file etc ...
end
end
initial begin
repeat(1000) begin
data_in = 'z; //stimulus read from file etc (no loop variable)...
end
end
NB: personally I would also add begin end to every thing to avoid adding extra lines later and wondering why they always or never get executed, especially while new to the language. It also has the added benefit of making the indenting look a little nicer.
always# (posedge CLOCK_50 or negedge reset_n) begin
if(!reset_n) begin
count <= 'b0;
end
else if (enable) begin
count <= count + 1;
end
end
Title
Error (10119): Verilog HDL Loop Statement error at : loop with non-constant loop condition must terminate within iterations
Description
This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.
Workaround / Fix
To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300
In Verilog HDL, how can I enforce that the rest of a register file to be untouched while I'm modifying a single bit? Like in the following example,
reg [31:0] result;
reg [31:0] next_result;
reg [4:0] count;
wire done;
//some code here...
result <= 32'b0;
always #* begin
if(done==1'b1) begin
next_result[count] <= 1'b1;
end
end
always #(posedge clock) begin
result <= next_result;
//the rest of the sequential part, in which count increments...
end
it turns out that result contains lots of x(unknown) values after several cycles, which means the register file is not held constant while I am modifying result[count]. Weird though, this problem is only present while I'm synthesizing, and everything goes just fine for simulation purposes. I wonder if there is some way to tell the synthesizer that I would like to "enforce" that not changing the rest of the register file.
You never assign all the bits inside the combinatorial loop. you have a floating assignment result <= 32'b0; I am surprised that this compiles. There is also an implied latch by not having next_result assigned in an else statement, ie when done=0 next_result would hold its value.
Try:
always #* begin
if(done==1'b1) begin
next_result = result;
next_result[count] = 1'b1;
end
else begin
next_result = result;
end
end
OR
always #* begin
next_result = result;
if(done==1'b1) begin
next_result[count] = 1'b1;
end
end
You have also used non-blocking <= assignments in the combinatorial loop.
I want to use if-else and for loop inside an always block. I don't want those if-else to be executed again and again, so I don't want to connect always with either posedge clkor negedge clk.
I want them to be executed only once. I not only want to simulate but I want to synthesize on to Spartan Board aswell.
always # (**what I should add here**)
begin
if(condition)
else
end
For simulations to execute some thing once you can use initial but this is not a synthesizable:
reg x;
initial begin
if(condition) begin
x = 1'b0 ;
end
else begin
x = 1'b1 ;
end
end
To answer the general question always #(**what I should add here**) Most modern verilog simulators will allow the use of * which will trigger the block (always begin to end) when any right hand side argument changes of any condition of selection logic.
always #* begin
if(condition)
x = y ;
else
x = ~y ;
end
older simulators would require you to list the variables you needed to trigger on, in a list. always #(condition, y)
If there is only 1 variable being selected an assign on a wire type might be better, but this can not be limited to being 'executed once', but would be a suitable choice from your question. Not sure about suitability for FPGA's though
wire [3:0] x ; //4 bit wire
//(condition) ? value if true : value if false ;
assign x = (condition) ? 4'b1010 : 4'b0100 ;
module oneShot(in, out, enable, reset);
input in;
input enable;
input reset;
output reg out;
reg once_only;
always # (posedge enable) begin
if (reset) begin
once_only <= 0;
end
else if (once_only == 0) begin
out <= calc_out; // or whatever processing you want
once_only <= 1;
end
end
always #(*) begin
// calculate ouput here always
calc_out = 1 + 7 +100+ in;
end
endmodule
You can't have those if statements calculate only once. It's hardware, it'll always calculate. But you can hold the output steady after it's been calculated once. You are still trying to write a software function and put it in to hardware rather than describe hardware which will solve your problem. I can't see that you'll get a decent design this way. Sure you'll be able to make some small pieces and synthesise them (eventually), but a full design??