Avoiding code repetition in Verilog - verilog

Question

I find that this happens too often in Verilog code:
wire my_module_output_1;
wire my_module_output_2;
wire my_module_output_3;
...
MyModule my_module(
.output_1(my_module_output_1),
.output_2(my_module_output_2),
.output_3(my_module_output_3),
...
);
MyOtherModule my_other_module(
.input_1(my_module_output_1),
.input_2(my_module_output_2),
.input_3(my_module_output_3),
...
);
What I wish I could do is:
MyModule my_module();
MyOtherModule my_other_module(
.input_1(my_module.output_1),
.input_2(my_module.output_2),
.input_3(my_module.output_3),
...
);
Is there any such way for me to achieve the same effect, i.e. to avoid having to repeat myself over and over again every time I need an output from some module wired somewhere?

Answer 1

Here are a few approaches you can use to reduce the amount of repetition.
The starting point
Here's a simple example that connects two sub-modules. As you noted in your question, there is a lot of repetition required to stitch them together.
module source(output A, output B);
assign A = 0;
assign B = 1;
endmodule
module sink(input A, input B);
initial begin
#1 $display("A=%0d B=%0d", A, B);
end
endmodule
module top();
wire A;
wire B;
source the_source(
.A(A),
.B(B)
);
sink the_sink(
.A(A),
.B(B)
);
endmodule
Using implicit wires
Verilog allows for wires to be declared implicitly. So, as shown below, you don't need to declare A and B as wires. If they appear in a port map, they will be implicitly declared. The only problem with this is that they are always declared as single-bit wires/nets. So while this works fine for single-bit signals, for buses the interconnect still needs to be explicitly declared.
// Verilog, implicit wires
module top();
source the_source(
.A(A),
.B(B)
);
sink the_sink(
.A(A),
.B(B)
);
endmodule
Using Verilog-Mode AUTOs
The Verilog-Mode emacs package can help tremendously in reducing the amount of typing required to stitch modules together. Here is the example from above using AUTOs.
Before expanding the AUTOs:
// Verilog, explicit connections using AUTOs
module top();
/*AUTOWIRE*/
source the_source (/*AUTOINST*/);
sink the_sink (/*AUTOINST*/);
endmodule
After expanding the AUTOs:
// Verilog, explicit using AUTOs
module top();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire A; // From the_source of source.v
wire B; // From the_source of source.v
// End of automatics
source the_source (/*AUTOINST*/
// Outputs
.A (A),
.B (B));
sink the_sink (/*AUTOINST*/
// Inputs
.A (A),
.B (B));
endmodule
As Brian pointed out in his answer, you don't need to use emacs to use Verilog-Mode. I also use Vim and use this Vim script to enable Verilog-Mode from within Vim.
SystemVerilog option
If you can use SystemVerilog, you can use the dot-star notation to connect ports by names. This is pretty handy but you still have to declare the wires for interconnects between peer modules.
// SystemVerilog, dot-star notation
module top();
wire A;
wire B;
source the_source(.*);
sink the_sink(.*);
endmodule

Answer 2

Are people still not using Verilog AUTOs everywhere?
http://www.veripool.org/wiki/verilog-mode/Verilog-mode-Help
In particular pay attention to the section on AUTOINST. This isn't going to solve all your problems but judicious use of AUTOs takes a lot of the tedium out of generating structural Verilog.
Don't mind that it's an Emacs node. I'm a vim guy myself but I just pipe my buffer through emacs with this mode loaded when I need my AUTOs updated.