How can I build a chain of modules? - verilog

Question

I am having trouble in building a chain of modules. I can connect models manually listing all the modules but need more concise representation. The following code has been tried but doesn't work? How can I correct the codes?
module network(
input signed [31:0] xi,
output signed [31:0] yo,
input clk,
input reset
);
wire signed [31:0] x0, x1, x2, y0, y1, y2, xo;
wire [3:1] t;
//working code for chain of pe
// pe u0(xi, x0, 0, y0, clk, reset);
// pe u1(x0, x1, y0, y1, clk, reset);
// pe u2(x1, x2, y1, y2, clk, reset);
// pe u3(x2, xo, y2, yo, clk, reset);
//chain of array not working! how!
pe p[1:4] ((xi,t), (t, x), (0, t), (t,yo),clk,reset); <- want to improve
endmodule
Here, pe (input,output,input,output,clk,reset).

Answer 1

Try this. It should work in all version of Verilog. In this instance the parameter PE_NUM must be an int with a value of 2 or more. A generate block must be use if a 1 pe instance is desired, which requires Verilog-2001 or SystemVerilog. Some simulators may have an hit a memory limitation when PE_NUM gets big (ex 2**16).
/*All Verilog*/
module network(
input signed [31:0] xi,
output signed [31:0] yo,
input clk,
input reset
);
parameter PE_NUM = 4; // limitation PE_NUM must be greater then 1
wire signed [31:0] xo;
wire signed [0:PE_NUM-2] [31:0] xN;
wire signed [0:PE_NUM-2] [31:0] yN;
pe p[0:PE_NUM-1] ({xi,xN}, {xN,xo}, {32'b0,yN}, {yN,yo}, clk,reset);
endmodule
The following is an example with generate:
/*Verilog-2001 or SystemVerilog*/
module network(
input signed [31:0] xi,
output signed [31:0] yo,
input clk,
input reset
);
parameter PE_NUM = 4; // no limitation
wire signed [31:0] xo;
generate
if(PE_NUM <2) begin
pe p (xi, xo, 32'b0, yo, clk,reset);
end
else begin
wire signed [0:PE_NUM-2] [31:0] xN;
wire signed [0:PE_NUM-2] [31:0] yN;
pe p[0:PE_NUM-1] ({xi,xN}, {xN,xo}, {32'b0,yN}, {yN,yo}, clk,reset);
end
endgenerate
endmodule