i am writting verilog code for shift left register which store its value after each shift in sub registers. can i define the output registers as array like this,the provided code is just a simple example to show the concept not my code,
module test(a,b,c);
input a,b;
output [7:0] c [3:0];
endmodule
instead of
module test(a,b,c1,c2,c3,c4);
input a,b;
output [7:0] c1,c2,c3,c4;
endmodule
and for the first way how i can call c[i]
... Yes you can very much use a 2D array at the output, like in your first example. Check out Section 5 of this paper by Stuart Sutherland himself, this should give you some confidence. The section is titled Module Ports.
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CC4QFjAA&url=http%3A%2F%2Fwww.sutherland-hdl.com%2Fpapers%2F2006-SNUG-Europe_SystemVerilog_synthesis_paper.pdf&ei=7KmYUNKPN6GyigKDnoHwDA&usg=AFQjCNGmr3flHrARC-w40xveo8zitcdjfg&cad=rja
Also, elaborating on your first example, you can define your module this way for clarity:
module lshift(clk, reset, a, c);
input wire clk, reset;
input wire [7:0] a;
output reg [7:0] c [0:3]; // <-- defining the unpacked dimension as [0:3] for clarity
always#(posedge clk) begin
if(reset) begin
c[0] <= 8'd0;
...
c[3] <= 8'd0;
end
else begin
c[0] <= a;
c[1] <= c[0];
c[2] <= c[1];
c[3] <= c[2];
end
end
endmodule
... and now you can slice into your array. c[0], c[1] .. c[3] each represents a Byte and c[0][3:0] would mean the lower nibble of the first byte.
... Hope this helps!
Related
Edit:Only by the screenshots(http://prntscr.com/lv3uqw http://prntscr.com/lv3yhf) and my code below you can still understand my goal here just incase you dont want to read the text.
I am trying to write a verilog code for a universal shift register. My original register was working properly(the one without the LR_bar signal). But on this one i have no idea how i can make this conection(mux with ff) happen http://prntscr.com/lv3uqw and http://prntscr.com/lv3yhf.I had a suggestion that the for loop should start from -1 but i still cant find a solution. I would also like to avoid the h signal if possible(maybe we also use the w there). So basicly when LR_bar=1 i want the shift register to shift left and when =0 to shift right.
Tip for the screenshot: ser in l_sh stands for serial input for left shifting
(Also found that on a Mano Morris 3rd edition(6th is more detailed) book (Computer Design Fundamentals) which is, to a point , a little close to what i want. But i want 2to1 multiplexers . But the 2 first screenshots is what i want to achieve.
http://prntscr.com/lvb5bt http://prntscr.com/lvb65f )
I think i describe it well...can someone solve this?
MY NEW CODE(below) AND TEST AFTER SOME VALUES......http://prntscr.com/lvhk63
I TRIED TO MIMIC THAT(http://prntscr.com/lvgx31 http://prntscr.com/lvgxgw http://prntscr.com/lvgxkw) BUT ONLY FOR THE SERIAL INPUT PART(MSB,LSB). PLEASE TELL ME WHERE IM WRONG. THANKS
the output should be the state of the register
-----------------------------------------------------------
module lr_shreg_n(in, out, clk, rst, LR_bar);
parameter n=4;
input in, rst, clk, LR_bar;
output [n-1:0] out;
wire [n+1:0] w;
wire [n-1:0] mux_out;
genvar i;
assign w[0]=in;
assign w[n+1]=in;
generate
for(i=0;i<n;i=i+1)
begin
mux2to1 MUX(.in({w[i],w[i+2]}),.sel(LR_bar),.out(mux_out[i]));
dff ff1(.d(mux_out[i]), .q(w[i+1]), .clk(clk),
.rst(rst));
end
endgenerate
assign out=w[n:1];
endmodule
------------------------------------------------------------
JUST AN ATTEMPT NOTHING TO LOOK
module lr_shreg_n(in, out, clk, rst, LR_bar);
parameter n=4;
input in, rst, clk, LR_bar;
output [n-1:0] out;
wire [n+1:0] w;
wire mux_out;
genvar i;
assign w[0]=in;
assign w[n+1]=in;
generate
for(i=-1;i<n-1;i=i+1)
begin
mux2to1 MUX(.in({w[i+1],w[3+i]}),.sel(LR_bar),.out(mux_out));
dff ff1(.d(mux_out), .q(out[i+1]), .clk(clk),
.rst(rst));
end
endgenerate
------------------------------------------------------------
module dff (d, q, clk, rst);
input d, clk, rst;
output reg q;
always # (posedge clk) begin : dff_block
if (rst==1'b1)
q = 1'b0;
else
q = d;
end
endmodule
module mux2to1(in, sel, out) ;
input [1:0] in;
input sel;
output reg out;
always #(*)
case(sel)
1'b0: out=in[0];
1'b1: out=in[1];
endcase
endmodule
module shreg_n(in, out, clk, rst);
parameter n=4;
input in, rst, clk;
output [n-1:0] out;
wire [n:0] w;
genvar i;
assign w[0]=in;
generate
for(i=0;i<n;i=i+1)
dff ff1(.d(w[i]), .q(w[i+1]), .clk(clk),
.rst(rst));
endgenerate
assign out=w[n:1];
//assign out=w[n];
endmodule
Blocking assignments might work in your specific case. As a matter of clean coding style and preventing any issues in the future, always use <= for all output assignments in flops (and latches).
Now, let's see what you want to do:
w = out; // to keep the immediate values and avoid ordering issues
for left shift: w[3] -> x, w[2] -> out[3], w[1] -> out[2], w[0] -> out[1] , in -> out[0]
for right shift: w[0] -> x, w[1] -> out[0], w[2] -> out[1], w[3] -> out[2], in -> out[3]
so, with a mux, say for out[2]i == 2, you would need a mux which does this:
- w[1] -
-> out[2]
- w[3] -
mux2to1 (.in({out[i+1], out[i-1]}), .sel(LR_sel), .out(out[i]));
you also need to take care of special cases [0] with left shift and [n-1] with the right shift. For simplicity,
you can use if statement in the generate block to handle it.
if (i == 0)
mux2to1 MUX0(.in({in, w[1]}), .sel(LR_bar), .out(tmp[0]));
else if (i == n-1)
mux2to1 MUXN(.in({w[n-2], in}), .sel(LR_bar), .out(tmp[n-1]));
.out(out[i]));
else
mux2to1 (.in({out[i-1], out[i+1]}), .sel(LR_sel), .out(out[i]));
Basically it creates yet another mux for those special cases, so that you have more of them.
As for the flop, there are at least 2 ways to approach it. You can flop results before or after the mux.
for the flopping before the mux (which i assumed in the above explanation), you just do
always #(posedge clk)
if (rst)
w <= 4'b0;
else
w <= out;
to do it after the mux, you would need to switch out and w and then flop w into out. You can do a bit-by-bit flop as you did, but it makes the program more crowded in my opinion. Also it causes verilog to generate multiple one-bit flops which might affect simulation performance.
Another approach for shift registers with the flop is to something like the following:
always #(posegde clk) begi
if (rst)
out <= 4'b0;
else if (LR_bar) begin
out <= {out[2:0], in};
end
else begin
out <= {in, out[3:1]};
end
end
The above simplifies the code significantly. BTW, you would have an issue if you use blocking assignments there.
Edit 1
I modified your code to a workable condition down here based on my comments.
you need a register w to keep the shift register value. You need the tmp to connect the mux with the flop. w is the output of the flop.
module uni_shreg_n(in, out, clk, rst, LR_bar);
parameter n=4;
input in, rst, clk, LR_bar;
output [n-1:0] out;
reg [n-1:0] w; // keep the value of the register shift
wire [n-1:0] tmp;
genvar i;
mux2to1 MUX0(.in({in,w[1]}), .sel(LR_bar), .out(tmp[0]));
mux2to1 MUXN(.in({w[n-2], in}), .sel(LR_bar), .out(tmp[n-1]));
generate
for(i=0;i<n;i=i+1) begin
if (i > 0 && i < n-1) begin: loop
mux2to1 MUX(.in({w[i-1], w[i+1]}), .sel(LR_bar), .out(tmp[i]));
end
dff ff1(.d(tmp[i]), .q(w[i]), .clk(clk), .rst(rst));
end
endgenerate
assign out = w;
endmodule
I want to create a shift register using d-flip-flop as basic structural element.
code:
dff:
module dff(d,q,clk,rst);
input d,clk,rst;
output reg q;
always #(posedge clk)
begin:dff_block
if(rst==1'b1)
q=1'b0;
else
q=d;
end
endmodule
shift register:
module shift_register(s1,d,clk,s0,q);
parameter n=3;
input s1,clk;
input [n:0] d;
output s0;
output [n:0] q;
genvar i;
assign d[3]=s1;
generate
for(i=0; i<=n; i=i+1)
dff U1(.d(d[i]),.q(q[i]),.clk(clk));
endgenerate
assign q[3]=d[2];
assign q[2]=d[1];
assign q[1]=d[0];
assign q[0]=s0;
endmodule
test bench:
module tb();
parameter n=3;
reg [n:0] d;
reg s1,clk;
wire [n:0] q;
wire s0;
shift_register UUT(.s1(s1),.d(d),.clk(clk),.q(q),.s0(s0));
initial begin
d=4'b0000;
clk=0;
end
always
begin:clok
#10 clk=~clk; s1=1;
end
endmodule
I think test bench has the problem.I have tried to give s1 values for every #10 while clk=1 but again does not work.
This code does not give me waveforms for q and s0.I cant find whats wrong.Any ideas?
you have several problems with the code.
q is an output reg of dff; q[i] is passed as q to dff. q[i] gets also assigned in within the assign statement. So, you have multiply driven wire q[i] which most likely gets resolved to x and never changes. You have your i/o swapped around somewhere.
you do not assign anything to s0, so it does not change and does not produce any waveform.
in this particular case blocking assignments within the flop will not pay any role, but in general they could cause unpredictable simulation results. Use non-blocking.
there is not much sense in the generate loop there. You can pass full vectors tot he dff and can flop full vectors as well.
It looks like you get confused int teh direction of the assign statement. It implies direction. assign q[0] = s0; means assign value of s0 to the wire q[0], not vice versa.
New Verilog user here. I was doing some exercises and needed to use some logic which made me wonder this. Here is some relevant code:
reg [7:0] a;
reg [0:7] b;
a[2] = 1'b1;
b[2] = 1'b1;
Would 'a' now be 00100000, or 00000100? I'm guessing 'b' would be 00100000, is that correct?
The range [7:0] means the MSB is 7 and the LSB is 0. So a would be 00000100
A few extra lines of code would give you your answer without needing to ask:
module top;
reg [7:0] a;
reg [0:7] b;
initial begin
a[2] = 1'b1;
b[2] = 1'b1;
$displayb(a,,b);
end
endmodule
This might seem like a very naive question, but I have just started working with Verilog (I use Xilinx ISE, if that helps).
I am trying to implement a shift register that shifts input PI by the value specified in the shft port. When I include the shifting logic in the RTL file, the shifting does not work, but when I move the always block corresponding to shifting to the testbench, it works. Please help me with this!
module shift (PI, shft, clk, PO);
input [7:0] PI;
input clk;
input [7:0] shft;
output reg [13:0] PO;
reg [7:0] shft_reg;
always #(posedge clk) begin
if (shft_reg[0]||shft_reg[1]||shft_reg[2]||shft_reg[3]||shft_reg[4]||shft_reg[5]||shft_reg[6]||shft_reg[7]) begin
PO <= {PO, 0};
shft_reg <= shft_reg-1;
end
end
endmodule
module shift (
input wire clk;
input wire load; // load shift register from input
input wire [7:0] PI;
input wire [7:0] shft; // this might need less bits
output wire [13:0] PO;
);
reg [7:0] shft_reg;
reg [13:0] value;
assign PO = value; // PO follows value
always #(posedge clk) begin
if (load) begin // initialize shift register and counter
shft_reg <= shft;
value <= {6'b0,PI};
end
else if (shft_reg) begin // if counter not reached end...
shft_reg <= shft_reg - 1; // decrement, and
value <= {value[13:1],1'b0}; // shift left value 1 bit
end
end
end
endmodule
Recall that Verilog supports the >> and << operators. For non-constants many-bit operands, this may be a waste of multiplexers, though:
module shiftcomb (
input wire [7:0] PI; // this value is left shifted
input wire [2:0] shft; // 0 to 7 bits positions
output wire [14:0] PO; // and is outputted to PO
);
assign PO = PI<<shft; // this will generate 15 mutlplexers:
// each one with 8 inputs, 3 bit select,
// and 1 output.
endmodule
Note that || is a logical or and idealy should be used with logical statments such as (shft_reg[0] == 1'b1 ) || ( shft_reg[1] == 1'b1).
Your if statment is really bitwise ORing all of the bits ie
shft_reg[0] | shft_reg[1] | shft_reg[2] | ...
You can use the OR Reduction operator :
|shft_reg
Your supplied code had typo'd PI for PO.
always #(posedge clk) begin
if (|shft_reg) begin
PO <= {PI, 0}; //PI input
shft_reg <= shft_reg-1;
end
end
I am having trouble putting this code together my main code is a state machine it adds 2 numbers together = sum then loads A to add A to sum(sum=a+sum) after clock is reached it then divides by n bit. I'm lost putting it together. In having Lots of trouble assigning outputs. what is legal and what is not am I able to set the regs equal to each other sometimes I feel like I can do that and some other times I cannot.if I use the module can the input be an output and vice versa I posted my whole code cause I wanted to get it to work. I think my device is correct but I need to create a test bench to tested.
module Adder (A1, B1, Cin,Q);
parameter n = 5;
output[n:0]Q;
reg [n:0]Q;
input [n:0] A1;
wire[n:0] A1;
input [n:0] B1;
wire [n:0] B1;
input Cin;
always #(A1 or B1 or Cin)
begin
Q = A1 +B1 + Cin;
end
endmodule
module ave(Clk,X,LA,DataA,Sum,Q);
parameter n=5;
input A,B,EB,Temp,DataA,DataB,Sum,Q;
input X;
reg A,B,Temp,Sum;
reg y,Y
wire
reg S1=3'b000;S2=3'b001;S3=3'b010;S4=3'b011;S5=3'b100;
always (Clk)
begin
case(y)
S1:
y=S2;
S2:
y=S3;
S3:
if (counter>0) y=S2;
else y=S4;
S4:
y=S4;
S5:
Done;
endcase
end
always (Clk)
begin
case
S1:
Counter=n; Temp=n; Sum=0;
S2:
A=X;
S3:
if (counter>0) B<=A+B;
else B<=B;
S4:
DataA=Temp;
DataB=Sum;
S5:
Done=1;
end
Adder add(A,Sum,Cin,Sum);
divider divid(Clk,1,1,1,1,DataA,DataB,1,1,Q,0);
endmodule
this is my divider plus the other modules:
module shiftlne(R,C,L,w,Clk,Q);
parameter n=8;
input [n-1:0]R;
input L,w,Clk,C;
output [n-1:0]Q;
reg [n-1:0]Q;
integer k;
always #(posedge Clk)
begin
if(L)begin
if(C)begin
Q<=R;end
else
begin
for (k=0;k<(n-1);k=(k+1))
Q[k+1]=Q[k];
Q[0]<=w;
end
end
end
endmodule
module downcounter (R,E,L,Clk,Q);
parameter n=8;
input[n-1:0]R;
input Clk,L,E;
output [n-1:0]Q;
reg[n-1:0]Q;
always #(posedge Clk)
begin if(L)
Q<=R;
else if(E)
Q<=(Q-1);
end
endmodule
module muxdff( D0, D1, Sel, Clk,Q);
input Clk,D0,D1,Sel;
wire D;
output Q;
reg Q;
assign D=Sel?D1:D0;
always # (posedge Clk)
begin
Q=D;
end
endmodule
module regne (R,Clk,Resetn,E,Q);
parameter n=8;
input [n-1:0]R;
input Clk,Resetn,E;
output [n-1:0]Q;
reg [n-1:0] Q;
always #(posedge Clk or negedge Resetn)
begin
if (Resetn==0)
Q<=0;
else if (E)
Q<=R;
end
endmodule
Are you stuck using Verilog-95 if not you can clean up the code style, if nothing else it helps spot the bugs easier.
NB: Uses spaces to indent your code, not tabs as they mess up the formatting when posting Q's and can look different to people review your code depending on how there editor is setup.
module Adder #(
parameter n = 5
)(
input [n:0] A1, //Inputs do not have to be declared as wires
input [n:0] B1,
input Cin,
output reg [n:0] Q;
);
//Auto sensitivity list with #* lowers chance of bugs
always #* begin
Q = A1 + B1 + Cin;
end
endmodule
Most languages, and I apply this to my verilog keep constants like parameters and localparam in UPPERCASE, everything else is lowercase.
Your shiftlne code be made more readable: readable code to me implies easier to spot the bugs and understand the design intention.
always #(posedge Clk) begin
if( L ) begin
if( C ) begin
Q <= R;
end
else begin
for (k=0;k<(n-1);k=(k+1))
Q[k+1] = Q[k]; //For loop only applies to this line
// should it not be Q[k+1] <= Q[k];
Q[0] <= w;
end
end
end
endmodule