Parameterized Bit-fields in verilog - verilog

Is it possible to parameterize a bit-field in verilog? Essentially I want to use a parameter or alternative to define a bit-range. The only way I can think of doing this is with a `define as shown below but it seems like there should be a better way.
`define BITFIELD_SELECT 31:28
foo = bar[BITFIELD_SELECT]

Parameters are nicer(safer) than defines since the namespace is not global to the project. You should be able to do this with two parameters.
parameter BITFIELD_HIGH = 31;
parameter BITFIELD_LOW = 28;
assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];
Alternatively
parameter BITFIELD_HIGH = 31;
localparam BITFIELD_LOW = BITFIELD_HIGH-3;
assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];

If you use macros (define) include the "`" when call the macro
`define BITFIELD_SELECT 31:28
foo = bar[`BITFIELD_SELECT]; // `BITFIELD_SELECT

Related

How to generate a string from a genvar value in a for loop?

Xilinx requires to define different group for IODELAY and IDELAY_CTRL. I want to parameterize my instances using generate and for loop.
I need to add a different string in the Verilog attribute (* IODELAY_GROUP = "GROUP_HERE" *)
How can I do that? I tried a lot using MACRO, functions without any success.
`define makegroup(x) `"GROUP_x`"
genvar h;
for (h=0;h<=3;h=h+1) begin:myfor
(* IODELAY_GROUP = {"GROUP_", h} *)
(* IODELAY_GROUP = `makegroup(h) *)
(* IODELAY_GROUP = {"GROUP_", $sformatf("%0h",h)} *)
end
Edit:
This solution {"IODELAY_GROUP_", h + 8'h30} doesn't work because it creates a logic bus instead of a string.
I want something that can be interpreted by the compiler not the synthesizer.
The solution does: (* IODELAY_GROUP = 144'h3X3X3X *) instead of (* IODELAY_GROUP = "GROUP_X" *)

Verilog RTL: Writing Digital data into predefined memory "address"

I have [8:0] digital data inputs. I want to pre-define these values and store them with a unique address so I can access them later in my logic by just calling their address value.
Not entirely sure, I was doing something like this (Also, this is for Verilog RTL (Syntheisizable):
reg array[8:0];
array[8] = 9'b000000000;
array[7] = 9'b000000001;
array[6] = 9'b000000010;
array[5] = 9'b000000011;
array[4] = 9'b000000100;
array[3] = 9'b000000101;
array[2] = 9'b000000111;
array[1] = 9'b000001000;
array[0] = 9'b000000000;
I'm not sure, this is just something that was on top of my head.
If youre looking to create a LUT (which is basically want you are suggesting), you are on the right track:
reg [8:0] lut [8:0]; // Its an array of 9 elements (0 through 8 after the variable name), each of which is 9 bits wide (before the variable name)
assign lut[8] = 9'b000000000; // If there is a pattern to the array, use generate statement and loops to initialize it, Im just doing it one-by-one here
assign lut[7] = 9'b000000001;
assign lut[6] = 9'b000000010;
assign lut[5] = 9'b000000011;
assign lut[4] = 9'b000000100;
assign lut[3] = 9'b000000101;
assign lut[2] = 9'b000000111;
assign lut[1] = 9'b000001000;
assign lut[0] = 9'b000000000;

Display all possible solutions in ojAlgo

Question: Is it possible to adjust the above to produce all possible results instead of an optimized one.
Details: Given a data set of armor, I want to produce a set of combinations where my constraints are fulfilled.
Variable helm1 = model.addVariable("Helm 1").binary();
Variable helm2 = model.addVariable("Helm 2").binary();
Variable helm3 = model.addVariable("Helm 3").binary();
Variable arm1 = model.addVariable("Arm 1").binary();
Variable arm2 = model.addVariable("Arm 2").binary();
Variable arm3 = model.addVariable("Arm 3").binary();
Expression statA = model.addExpression().lower(0).weight(1);
Expression statB = model.addExpression().lower(0).weight(1);
Expression statC = model.addExpression().lower(0).weight(1);
//Lower Limit set for desired stat
Expression statD = model.addExpression().lower(2).weight(1);
// Limit number of helms you can equip
model.addExpression().upper(1).set(helm1,1).set(helm2,1).set(helm3,1);
model.addExpression().upper(1).set(arm1,1).set(arm2,1).set(arm3,1);
statA.set(arm1, 1);
statB.set(helm2, 1);
statB.set(helm3, 1);
statB.set(arm2, 1);
statC.set(helm1, 1);
statC.set(arm2, 1);
statC.set(arm3, 1);
statD.set(helm3, 3);
statD.set(arm1, 1);
Optimisation.Result result = model.maximise();
BasicLogger.debug(result);
Note: Before recommending libraries, please not that the library must be compatible with Android.
Answer: No - ojAlgo will output 1 (the optimal if it can find it) solution.

Store multiple variables as a single hex string

I am looking for a way to store a few variables in one variable so I can output a string. For example, I have variables:
int flow_val = "128";
int numb_val = "104";
int size_val = "256";
I can put them together using $display like this:
$display("32'h%0h%0h_%4h", flow_val, numb_val, size_val);
to print out:
32'h8068_0100
Is there a way to get that output and put it into a variable such as hex_val?
$sformatf can be used. Refer to IEEE Std 1800-2012, section 21.3.3 Formatting data to a string.
module tb;
int flow_val = 128;
int numb_val = 104;
int size_val = 256;
string hex_val;
initial begin
hex_val = $sformatf("32'h%0h%0h_%4h", flow_val, numb_val, size_val);
$display(hex_val);
end
endmodule
Output:
32'h8068_0100

NDepend rule to warn if objects of a given type are compared using ==

as the title says: I need a NDepend rule (CQLinq) for C#/.net code, that fires whenever instances of a given type are compared using == (reference comparison). In other words, I want to force the programmer to use .Equals.
Note that the type in question has no overloaded equality operator.
Is this possible? If so, how? :)
Thanks, cheers,
Tim
With the following code with see that for value type, == translate to the IL instruction: ceq. This kind of usage cannot be detected with NDepend.
int i = 2;
int j = 3;
Debug.Assert(i == j);
var s1 = "2";
var s2 = "3";
Debug.Assert(s1 == s2);
However for reference types we can see that a operator method named op_Equality is called.
L_001d: call bool [mscorlib]System.String::op_Equality(string, string)
Hence we just need a CQLinq query that first match all method named op_Equality, and then list all callers of these methods. This can look like:
let equalityOps = Methods.WithSimpleName("op_Equality")
from m in Application.Methods.UsingAny(equalityOps)
select new { m,
typesWhereEqualityOpCalled = m.MethodsCalled.Intersect(equalityOps).Select(m1 => m1.ParentType) }
This seems to work pretty well :)

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