I need to split a two-digit number up so that I can display them separately. The problem is that mod only works with numbers that are a power of 2. How can this be done?
From http://www.edaboard.com/thread112872.html
Many synthesis tools don't support
integer division/modulus/remainder
unless the calculation is trivial,
such as division by a power of two. If
your value isn't a power of two, then
you are probably out of luck.
Maybe you can use another approach
such as building your own math module,
or using a math core from your
software's IP library.
Or maybe you can approximate the
division by multiplying by the
fraction 1/K instead of dividing by K.
If both operands are small, you could
fetch the result from a ROM lookup
table.
If this is a simple incrementing value, you should consider Binary Coded Decimal counters. You need 4 bits per digit but it makes interfacing with 7-segment displays much easier.
//BCD counter - I did not test this
reg [3:0] digit_one, digit_two;
always #(posedge clk)
begin : led_digits
if(reset)
begin
digit_one <= 0;
digit_two <= 0;
end
else if(increment)
begin
//BCD values wrap at 9
if(digit_one == 4'd9)
digit_one <= 0;
else
digit_one <= digit_one + 1;
//Carry when previous digit wraps
if(digit_one == 4'd9)
begin
if(digit_two == 4'd9)
digit_two <= 0;
else
digit_two <= digit_two + 1;
end
end
end
If you have some arbitrary decimal value you need to display, then it gets more complicated. GuanoLoco's solution should work for a 2 digit output. A more efficient algorithm exists but the implementation is not as straightforward.
A simple brute force solution would be to use an if-else block to compare your number to multiples of 10. The largest multiple of ten that is smaller than your number is the "tens" digit, and the difference is the "ones" digit.
if (number >= 90) begin
tens <= 9;
ones <= number - 90;
end else if ...
That said, this isn't scalable, and giant if-else blocks are generally not good practice.
Rather confusinq question. When you say "display", I immediately think $display, hence modeling and simulation. There are no powers of 2 restrictions on modulo for modeling purposes.
But even if you mean synthesis, it is not true in general that modulo only works with powers of 2. However, doing this is probably not a very good idea, because it would be quite expensive in hardware.
Related
I will give a small snippet of what I mean:
input [31:0] for_terminate;
for(i = 0; i < for_terminate; i = i + 1)
....
Clearly, this is a small piece of code, but I think it illustrates my idea. Is this possible?
I assume you actually ask: can this be synthesized. The answer is NO.
A for loop is unrolled in compile time. (See also here ) As such the start, increment and end value must be known when you compile. This also means it is good practice to limit your for loop range. The following code is legal, can be synthesized, but will not fit in your FPGA or ASIC:
for (i=0; i<4294967296; i=i+1)
begin
// Make some logic
...
You can make the equivalent with an if:
for (i=0; i<MAXIMUM_LOOP; i=i+1)
begin
if (i<for_terminate)
begin
...
The logic for all MAXIMUM_LOOP cases will be generated, but each will have a condition which checks the value of for_terminate. Seeing that your for_terminate is 32 bits wide, I think you should limit that somewhat.
In Verilog/VHDL, lets say I have a 4 bit counter, and a flag that should be asserted when the counter equals between 4 and 8. There are two ways to implement this
if((cntr>=4)&&(cntr<8))
flag <=1;
else
flag <= 0;
Or, I could do this
if(cntr==4)
flag<=1;
else if (cntr==8)
flag<=0;
It seems to me that functionally, these do the same thing.
Is there any reason one would be better than the other? style-wise? How about for synthesis/implementation?
In both examples, flag will be synthesised as a flip-flop. This is because (I assume) you are driving it from within a clocked always block, ie your two examples are:
always #(posedge clk)
if ((cntr>=4)&&(cntr<8))
flag <= 1;
else
flag <= 0;
and
always #(posedge clk)
if (cntr==4)
flag <= 1;
else if (cntr==8)
flag <= 0;
Both examples are simple (2-state) FSMs. There is little to choose between them. Both will be implemented by a flip-flop (flag) whose D-input is driven by a small amount of combinational logic. The only difference is that that combinational logic may be smaller with the second example than the first because implementing == generally requires less area than implementing < or >.
I am trying to use the 8 switches on my basys2 board to control the frequency of a square wave, yet I'm having trouble with the input part of it, as I do not know how to divide the clock using the binary value of the register that I have collected the states of the switches in.
I know that I need to divide 25000000/[input value] in order to get the correct value for the counter. My question is:
how can I divide 25000000 by the register which has the switch states stored inside of it such, as input [7:0] SW?
If you can assume your input is always a power of two, you can use shifting to the right. But if you want the full 255 possible resolutions, you need to implement a divider.
Some synthesis tools just synthesize a divider when you simply write 25000000/inputValue. For some others, you may have to do it yourself.
Alternatively, if you don't want to waste time for dividing, you can pre-calculate the values beforehand and use a counter:
case (inputValue)
8'b0000_00010: counterMax = 25000000/2 ; //Where 25000000/2 can be calculated at compile time or by you
8'b0000_00011: counterMax = 25000000/3 ; //Where 25000000/3 can be calculated at compile time or by you
...
endcase
and then just count to the counterMax:
always #(posedge clock)
begin
counter <= counter + 1;
if(counter == counterMax) begin
out <= ~out;
counter <= 0;
end
end
Instead of dividing by input, can you just increment your counter by SW each clock cycle? Then if SW is for example, '15', then your period is reduced by 15x, but you avoid an expensive division circuit.
This may seem like a rather stupid question, but the transition from software to HDL's is sometimes rather frustrating initially!
My problem: I have an array multiplication I am trying to accomplish in Verilog. This is a multiplication of two arrays (point by point) which are of length 200 each. The following code worked fine in the testbench:
for (k=0; k<200; k=k+1)
result <= result + A[k] * B[k];
But it doesn't even come close to working in the Verilog module. I thought the reason was because the operation should take place over many many clock cycles. Since it involves writing out 200 multiplications and 199 additions if I do it by hand (!), I was wondering if there was a trick in making the for loop work (and be synthesizable)?
Thanks,
Faisal.
You don't want to use a for loop there, you want to use a block of clocked logic. For loops are only for describing parallel structures that don't feedback on themselves, they are only rarely useful and not for the same kinds of things you would use them for in a software program.
To do what you're trying to achieve, you should have a block like so:
always #(posedge clk or posedge reset)
if (reset) begin
result <= 0;
k <= 0;
result_done <= 0;
end else begin
result <= result_done ? result : (result + A[k] * B[k]);
k <= result_done ? k : k + 1;
result_done <= result_done ? 1 : (k == 200);
end
end
This zeros the result on reset, adds A[k] * B[k] to a sum for 200 clocks, and then stops counting when k == 200 and asserts a 'done' signal.
I'm trying to slow a 50MHz clock down to 25.175MHz for use in a VGA controller. I have a clock divider already, but am having trouble slowing the clock down whenever the resulting division of the current clock speed and the desired clock speed is not a whole number. I.E. 50000000/25175000 ~ 1.98. The clock divider compiles and runs, but outputs nothing if the division is a decimal number. Here's my code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Clockdiv IS PORT (
Clkin: IN STD_LOGIC;
Clk: OUT STD_LOGIC);
END Clockdiv;
ARCHITECTURE Behavior OF Clockdiv IS
CONSTANT max: INTEGER := 50000000/25175000;
CONSTANT half: INTEGER := max/2;
SIGNAL count: INTEGER RANGE 0 TO max;
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clkin'EVENT and Clkin = '1';
IF count < max THEN
count <= count + 1;
ELSE
count <= 0;
END IF;
IF count < half THEN
Clk <= '0';
ELSE
Clk <= '1';
END IF;
END PROCESS;
END Behavior;
I searched on google, and found using the REAL data type will allow you to use decimals, but when I changed the variables I'm using to REALs, Quartus gives me the error: Error (10414): VHDL Unsupported Feature error at Clockdiv.vhd(12): cannot synthesize non-constant real objects or values.
Then, if I change "count" to a CONSTANT type, I get the error: Error (10477): VHDL error at Clockdiv.vhd(18): name "count" must represent signal.
Does anybody know how I can slow a clock down to 25.175MHz? Also, does anybody know how to slow a clock down so that the compiler is happy with the resulting division being a decimal value?
Thanks
Reals are, in general, not synthesisable, so you'll need to come up with an integer based solution.
That ratio is quite a tricky one because it's almost 2:1, but not quite. Most edge based clock divider circuits work only on one edge of the original clock, so the lowest ratio you can divide by is 2. In this case you'll have to work on both edges of the clock.
Once you've got that you need to have a counter that increments by the denominator of your ratio and is it's over the numerator then output a clock edge.
PROCESS
BEGIN
WAIT UNTIL Clkin'EVENT;
IF count < max THEN
count <= count + DENOMINATOR;
ELSE
count <= 0;
END IF;
IF count > NOMINATOR THEN
Clk <= ~Clk;
END IF;
END PROCESS;
For this ratio I think the smallest way you can represent it is 2000/1007.
The trouble with this is that you'll get a clock that's basically 25MHz, but occasionally (each 2000 / 7 iterations) you'll get an extra edge. It won't be a 25.175MHz clock. Getting 25.175MHz from 50MHz is impossible without a PLL.
I've written plenty of VGA controllers, and just using a 25 MHz clock has never been much of a problem. If you absolutely want to get closer though, your FPGA probably has a clock manager of some sort (I'm only familiar with Xilinx devices), that will allow you to synthesize an output clock by multiplying and dividing an input clock.
Also, while using derived/gated clocks (clocks where you directly set the value in a process) will probably work for you in this case, it can lead to a lot of problems that can be hard to debug. A better solution is to generate clock enables, and then run everything on the same (fast) clock.
And a last thing, although it is probably as much a question of preferred style, but I usually use clocked process statements instead of WAIT statements (shown below with rising edge trigger, synchronous reset and a clock enable). I find it clearer to read and understand, and less prone to writing unsynthesizable constructs such as wait for 10ns;, or statements with multiple WAITs.
process(clk)
begin
if(rising_edge(clk)) then
if(sync_reset = '1') then
--Reset logic
elsif(clk_enable = '1') then
--Actual functionality
end if;
end if;
end process;