I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:
reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;
neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?
(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)
When using assign you should declare the array as a wire instead of areg.
Since your goal is to design an FSM, there is no need to store the state values in an array. This is typically done using Verilog parameter's, a state register and a next_state with a case/endcase statement.
The following paper shows a complete example: FSM Fundamentals
If this is targeted towards synthesis:
A little beyond what was answered above, there are standard FSM coding styles that you should adhere to so the tools can perform better optimization. As described in the Cummings paper, one-hot is usually best for FPGA devices and in fact ISE(with default settings) will ignore your encoding and implement whatever it thinks will best utilize the resources on the device. This almost invariably results in a one-hot encoded FSM regardless of the state encoding you chose, provided it recognizes your FSM.
OK, so to answer your question, let's dig a little deeper into Verilog syntax.
First of all, to specify a range of bits, either do [MSB:LSB] or [LSB:MSB]. The standard is MSB:LSB but it is really up to you here, but try to be consistent.
Next, in array instantiation we have:
reg WIDTH reg_name NUMBER;
where WIDTH is the "size" of each element and NUMBER is the number of elements in the array.
So, you first want to do:
reg [7:0] transitionTable [7:0];
Then, to assign particular bytes (8 bits = 1 byte), do:
initial begin
transitionTable[0] = 8'h10;
end
A good book to learn Verilog from is FPGA Prototyping By Verilog Examples by Pong P. Chu.
Related
Consider this
reg [5:0]assign_me;
reg [11:0]source_of_data;
assign_me <= source_of_data[5:0];
where assign_me always gets the least significant bits of source_of_data. Here the 5 is hardcoded in the last line in the sense that if for some reason the definition of assign_me changes to reg [6:0]assign_me I will have to change the last line. Is there any way to avoid this? Like for example in a pythonic notation something like assign_me <= source_of_data[:0]?
You could use:
assign_me <= source_of_data;
Verilog will assign the LSB's. But, you might get warnings about width mismatch.
A cleaner way is to use a parameter:
parameter WIDTH = 6;
reg [WIDTH-1:0]assign_me;
reg [11:0]source_of_data;
assign_me <= source_of_data[WIDTH-1:0];
When it comes to integral (packed) arrays, Verilog is loosely typed. Verilog will right justify to align LSBs, then make the assignment padding or truncating the MSB. You do not need to select a specific set of bits unless you need to mask bits on either end. Some tools will generate size mismatch warnings, especially around port connections, but the language does not require it.
One thing to be careful of is that selecting bits of a single is always unsigned regardless of the sightedness of the signal as a whole.
So in order to load memory into a "file" on the FPGA I am using the procedure outlined here.
The rough formula is this
reg [7:0] ex2_memory [0:15];
$readmemh("ex2.mem", ex2_memory);
Which is strange to me because a lot of guides suggest it should be slightly different. For example this was in one of my guides
Sometimes it can be useful to have structures with more than one dimension – for example, we might want to hold 16 8-bit values. Verilog allows you to define multiple sets of indexes for a variable:
reg [7:0] string [15:0];
Notice how there it is [n:0] instead of [0:n] in the readmemb example. So what is the difference between these two ways of defining this multidimensional bus?
For Verilog, the unpacked dimension order does not matter. $readmemh/b always maps the starting address to the lower index, and you can only access one memory element at a time. There is a rare exception for C code when using the Verilog Programming Interface (VPI), but did I say that was rare?
In SystemVerilog it matters more because you can access unpacked arrays as a whole or use part selects similar to the way Verilog allows part selects of packed vector dimensions. It makes a difference between reg [7:0] mr; or reg [0:7] mr; when you select bit mr[0].
I always thought that bus notations is annotated like this:
input bus[MSB:LSB]
where MSB >= LSB.
But recently, I was told that even this is possible:
wire LSB >= MSB.
Is it even true?
If so, then how come synthesizer tools get the bus size and all? Do they consider that whichever index is big is MSB?
Yes, both directions of bit numbering could be used in declarations. However, the same ordering must be used when you do bit selection. For example
wire [0:15] bus;
reg [15:0] data;
assign bus [3:6] = data[3:0];
In most cases through industry the second notation is used (msb > lsb) and it is encouraged for consistency reasons. However in some situations it is convenient to do the opposite.
The bit numbering does not matter until you select a single bit or part select of the bus. As long as you know how the signal is declared any tool can figure out the bit width and msb ordering
I initialize a register
reg[1:0] yreg;
and manipulate it a bit, i.e., value from prev. iteration of program is shifted to 1 spot when I add in the new value in the 0 spot
yreg = SIGNAL; //here SIGNAL is an input to the program
And then I want to access the values at the 0 and 1 spots in the register later for a calculation. How can I do this? My initial reaction was yreg[0] and yreg[1] (I normally program in python =) but this is producing an error (line 35 is the line of code that has yreg[0] and yreg[1] in it):
ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 35: Syntax error near "[".
My assumption when I saw this was that it's not the right syntax to use the brackets to access a certain index of the register. How do you properly access the information in an index of a register? I'm having trouble finding information on this.
Sorry for the probably ridiculous question, this is my first time ever using verilog or FPGAs in general.
Full Code
module trapverilog(
input CLK,
input SIGNAL,
input x,
output OUT
);
reg[1:0] yreg;
float sum = 0;
always #(posedge CLK)
begin
yreg = SIGNAL; //should shift automatically...?
sum = ((reg[0] + reg[1])*x/2) + sum; //this is effectively trapezoidal integration
OUT = sum;
end
endmodule
You have a fundamental misunderstanding of how Verilog signals work.
By default, all Verilog signals are single bits. For example, in your code, SIGNAL, x, and out are all one bit wide. They cannot store a number (other than 0 or 1).
Specifying a width when you define a signal (like reg [1:0] yreg) controls how many bits are used to represent that signal. For instance, yreg is a two-bit signal. This does not mean that it "shifts automatically"; it just means that the signal is two bits wide, allowing it to be used to represent numbers from 0 to 3 (among other things).
I would strongly advise that you work through a course in digital electronics design. Verilog programming is very different from procedural programming languages (such as Python), and you will have a hard time making sense of it without a solid understanding of what you are actually building here.
Apparently as per this answer using brackets to get a certain index of a register is correct. I just forgot to call the variable properly - I was calling reg[0] instead of yreg[0]. Changing this fixed the error.
I am programming with Xilinx's vivado in verilog.
I was wondering why for some outputs we use reg
For example reg [3:0] encoder_output
we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to "STORE SOMETHING"
Is my idea right??
It's not actually a stupid question, despite all the downvotes. In The Beginning, The Designer created nets and registers. Nets were intended as connections between hardware elements, and had values driven onto them; they didn't hold those values. Nets are normally declared as wire. Registers were data storage elements, and did hold a value; they are normally declared as reg. Over time, it became clear that this division (which sort-of-looks-like "hardware") doesn't make sense, and at least one proposal was made to drop the net/register distinction from the language. This never happened (unless you consider SystemVerilog to be 'Verilog', which I don't).
So, your question made sense 30 years ago, and your answer would have been "correct".
However, in practice, it doesn't matter which you use. The real distinction is that you can only assign to a reg from within sequential code (always/etc), and to a wire otherwise. This requirement is completely arbitrary and only exists for historical reasons. You just need to learn the rules.