Permuation in SystemVerilog using genvar - verilog

Question

I am working on a piece of code for permutation. I could not find a nice of assigning signals indexed with genvar and an input.
I have input i with array of 4, and output o again with same size. And I have a permutation index. Depending on the permutation index, I want to assign outputs to inputs such as:
perm_index 0 | o[0] <- i[0] | o[1] <- i[1] | o[2] <- i[2] | o[3] <- i[3]
perm_index 1 | o[0] <- i[1] | o[1] <- i[0] | o[2] <- i[3] | o[3] <- i[2]
perm_index 2 | o[0] <- i[2] | o[1] <- i[3] | o[2] <- i[0] | o[3] <- i[1]
perm_index 3 | o[0] <- i[3] | o[1] <- i[2] | o[2] <- i[1] | o[3] <- i[0]
This is the permutation that I want to code, and I want to use genvar for this. In my coding with genvar g and input [1:0] perm_index, this line o[g].addr <= i[g^perm_index].addr; causes an error "perm_index is not a constant".
Does anyone knows a better way to write this code?
First I coded my permutation using a generate block, such as:
genvar g;
generate
for (g=0; g<4; g++)
always_comb
o[g].addr <= i[g^perm_index].addr;
endgenerate
However, Vivado does not accept this code, throwing out an error "perm_index is not a constant".
I could solve it by writing the code as shown below.
genvar g;
generate
for (g=0; g<4; g++)
always_comb
case (g[1:0])
(2'd0^perm_index) : o[g].addr <= i[0].addr;
(2'd1^perm_index) : o[g].addr <= i[1].addr;
(2'd2^perm_index) : o[g].addr <= i[2].addr;
(2'd3^perm_index) : o[g].addr <= i[3].addr;
endcase
endgenerate
Although this is a solution, I am not happy with this coding style. Does anyone knows a better way to write this code?

Answer 1

It looks lie you are trying to implement some weird bit swapping. I kind of guess what it is but straight forward implementation for this example is much easier than an attempt to create a clever algorithm for it.
In any case, you do not need any generate statement at all. It is a special construct and it is supposed to be used for configuration purposes or algorithmic instantiation of multiple design elements. You do not have either.
So, I tried to follow your picture and created a possible implementation with a 'case' statement as the following:
module perm(input logic[1:0] perm_index, input logic[3:0]i, output logic [3:0] o);
always_comb begin
case(perm_index)
0: o = i;
1: o = {i[1], i[0], i[3], i[2]};
2: o = {i[2], i[3], i[0], i[1]};
3: o = {i[3], i[2], i[1], i[0]};
endcase
end
endmodule
I do not think that you can get it easier than that, unless you have much bigger vectors.
And here is a simple test bench
module top;
logic [3:0] perm_index;
logic [3:0] i, o;
perm perm(perm_index, i, o);
initial begin
$monitor("%0t> %0d: %b --> %b", $time, perm_index, i, o);
i = 4'b1100;
for (int pi = 0; pi < 7; pi++) begin
perm_index = pi;
#2;
end
#2 $finish;
end
endmodule
As it turned out, OP used System Verilog interfaces. Below is an example with interfaces.
First is a straight forward one with concats:
module perm(input logic[1:0] perm_index, I i[4], I o[4]);
always_comb begin
case(perm_index)
0: {o[0].addr, o[1].addr, o[2].addr, o[3].addr} =
{i[0].addr, i[1].addr, i[2].addr, i[3].addr};
1: {o[0].addr, o[1].addr, o[2].addr, o[3].addr} =
{i[1].addr, i[0].addr, i[3].addr, i[2].addr};
2: {o[0].addr, o[1].addr, o[2].addr, o[3].addr} =
{i[2].addr, i[3].addr, i[0].addr, i[1].addr};
3: {o[0].addr, o[1].addr, o[2].addr, o[3].addr} =
{i[3].addr, i[2].addr, i[1].addr, i[0].addr};
endcase
end
endmodule
Here is one with genblocks:
module perm(input logic[1:0] perm_index, I i[4], I o[4]);
parameter int perm_i[4][4] = '{
'{0, 1, 2, 3},
'{1, 0, 3, 2},
'{2, 3, 0, 1},
'{3, 2, 1, 0}};
for (genvar v = 0; v < 4; v++) begin
always_comb
case (perm_index)
0: o[v].addr = i[perm_i[0][v]].addr;
1: o[v].addr = i[perm_i[1][v]].addr;
2: o[v].addr = i[perm_i[2][v]].addr;
3: o[v].addr = i[perm_i[3][v]].addr;
endcase
end
endmodule
And an updated testbench
interface I;
logic[3:0] addr;
endinterface
module top;
I i[4]();
I o[4]();
logic [3:0] perm_index;
perm perm(perm_index, i, o);
initial begin
$monitor("%2t> [%0d], i(%0d,%0d,%0d,%0d) --> o(%0d,%0d,%0d,%0d)",
$time, perm_index,
i[0].addr, i[1].addr, i[2].addr, i[3].addr,
o[0].addr, o[1].addr, o[2].addr, o[3].addr);
{i[0].addr, i[1].addr, i[2].addr, i[3].addr} = {4'd1, 4'd2, 4'd3, 4'd4};
for (int pi = 0; pi < 7; pi++) begin
perm_index = pi;
#2;
end
#2 $finish;
end
endmodule

Answer 2

Permutation is possible with gen var. What you aree trying to achieve is actually a rotation. You can obtain it with modulo operation.
It is possibile provided that perm_index is a constant value, eg: parameter.
It is good practice to have a constant width value for array size. I show a full example:
module top;
parameter logic[1:0] PERM_INDEX=0;
parameter ARRAY_W= 4;
typedef struct{
int addr;
} my_t;
my_t i[ARRAY_W];
my_t o[ARRAY_W];
initial begin;
for(int j=0; j<ARRAY_W; j++) begin
i[j].addr = j+ 10;
$display("i[%d].addr = %d", j, i[j].addr);
end
#10;
for(int j=0; j<ARRAY_W; j++) begin
$display("o[%d].addr = %d", j, o[j].addr);
end
end
genvar g;
generate
for (g=0; g<ARRAY_W; g++)
assign o[g].addr = i[(g+PERM_INDEX)%ARRAY_W].addr;
endgenerate
endmodule
------------------ EDIT ------------
To have perm_index changing over the time, the best approach is to use a barrel shifter.
https://en.wikipedia.org/wiki/Barrel_shifter
Already answered here:
How can i make my verilog shifter more general?