I'm very new to verilog and not sure what data types to use. I'm trying to iterate over a binary number and xor each bit. I can do this manually, but I can't store it into a different reg.
module iterator(a, b);
input [3:0] a;
input [3:0] b;
integer i = 0;
reg [3:0] c = 4'b0000;
always # (a or b) begin
$display("p = %b", p);
for(i = 0; i < 4; i=i+1)
c[i] = a[i] ^ b[i];
$display("i = %d, a[i] = %b, b[i] = %b, a[i] ^ b[i] = %b", i, a[i], b[i], c[i]);
end
endmodule
module Testbench;
reg [3:0] a = 4'b1001;
reg [3:0] b = 4'b0110;
iterator it(a, b);
endmodule
Just to point out:
1: your display statement is misaligned. It is not inside the for loop. (This is not python thank god!) Use:
for(i = 0; i < 4; i=i+1)
begin
c[i] = a[i] ^ b[i];
$display("i = %d, a[i] = %b, b[i] = %b, a[i] ^ b[i] = %b", i, a[i], b[i], c[i]);
end
2: there is no variable 'p' which suggest this is not the code you used (syntax error).
3: Your code has no output. You EXOR bits but return no result as you have no output port.
4: initialising c to 4'b0000 is not always synthesize-sable. It is a bad habit and should be avoided unless it is strictly necessary. (Which is not here).
But all that goes away if you use toolic's code.
In order for the code inside an always block to be executed, you need to make sure that the values of the variables in sensitivity list are changed. In your example you need a test bench to do so.
In your always block a and b are the signals which trigger execution of the code inside the block, if any of them changes.
always # (a or b) begin
$display("p = %b", p);
To do provide such a change you can do something like the following:
module Testbench;
reg [3:0] a;
reg [3:0] b;
iterator it(a, b);
initial begin
a = 4'b1001;
b = 4'b0110;
#2
a = 4'b0110;
b = 4'b1111;
#2
...
end
endmodule
Related
I have a data of 1024 bit stored in A register.
reg [1023:0] A;
reg [7:0] B [0:127]
Now I want to convert it into 2 dimensional register B. How's it possible with minimum coding in Verilog?
In System Verilog a streaming operator could be used for this:
module top;
reg [1023:0] A;
reg [7:0] B [0:127];
always_comb begin
B = {>>{A}};
// this also works:
// {>>{B}} = A;
end
// testing
initial begin
for(int i = 0; i < 128; i++)
A[i*8 +: 8] = i;
#1 $finish;
end
always #* begin
$display("A: %3d %3d %3d", A[7:0], A[15:8], A[1023:1016]);
$display("B: %3d %3d %3d", B[127], B[126], B[0]);
end
endmodule
Just note, due to the B[0:127] declaration, index [0] is the most significant one and maps to A[1023:1016]. If you want an opposite mapping, declare B[127:0].
One way is to use a for loop:
module tb;
reg [1023:0] A;
reg [7:0] B [0:127];
always_comb begin
for (int i=0; i<128; i++) begin
B[i] = A[8*i +: 8];
end
end
endmodule
See also +:
I've written a code for matrx multiplication in Verilog.
module multiply3x3(i1,i2,i3,i4,i5,i6,i7,i8,i9,j1,j2,j3,j4,j5,j6,j7,j8,j9,prod);
output reg [31:0]prod;
wire [7:0]resultant[3:0][3:0];
wire [7:0]a[3:0][3:0];
wire [7:0]b[3:0][3:0];
genvar i,j,k;
generate
for (i = 0; i <= 2; i=i+1) begin:i_
for (j = 0; j <= 2; j=j+1) begin:j_
assign resultant[i][j] = 8'd0;
for (k = 0; k <= 2; k=k+1) begin:k_
assign resultant[i][j] = resultant[i][j] + a[i][k] * b[k][j];
end
end
end
endgenerate
endmodule
initial begin
#100 prod = {resultant[0][0],resultant[0][1],resultant[0][2],resultant[1][0],resultant[1][1],resultant[1][2],resultant[2][0],resultant[2][1],resultant[2][2]};
end
This is where the multiplication happens, but i cannot get the output for this.
What am I doing wrong?
consider a,b declared properly.
Accumulation (a = a + p) doesn't work with wires. The type wire is supposed to model a physical wire.
You'll have to declare the variable resultant as a reg. The reg type, in Verilog, can in some cases be treated like a variable in other programming languages.
Also, you can't use the assign statement on a wire or reg multiple times (like you've done in line 78 and 80 of https://pastebin.com/txrcwUBd). You should use always (and not generate) blocks to perform such things.
Corrected Verilog:
reg [7:0] resultant[3:0][3:0];
int i, j, k;
always #(*)
for(i=0; i<3; i=i+1)
for(j=0; j<3; j=j+1) begin
resultant[i][j] = 8'd0;
for(k=0; k<3; k=k+1)
resultant[i][j] = resultant[i][j] + (a[i][k]*b[k][j]);
end
I need to program a sequential circuit in Verilog code as a pattern generator which generates, instead of binary counts, your Firstname (space) Lastname (space), character by character. I need to display the pattern sequence for at least two cycles.
diagram
This is the sample output:
sampleoutput
I know that the issue my program has is in the CoderMod module, but I'm not sure where the issues are.
Thanks for the help!
//pattern.v
module TestMod;
reg CLK;
wire [0:11] Q;
wire [6:0] ascii;
initial begin
#1;
forever begin
CLK=0;
#1;
CLK=1;
#1;
end
end
RippleMod my_ripple(CLK, Q);
CoderMod my_coder(Q, ascii);
initial #27 $finish;
initial begin
$display("Time CLK Q Name");
$monitor("%4d %b %b %c %x %b", $time, CLK, Q, ascii, ascii, ascii);
end
endmodule
module CoderMod(Q, ascii);
input [0:13]Q;
output [13:0] ascii;
assign ascii[0] = "F";
assign ascii[1] = "i";
assign ascii[2] = "r";
assign ascii[3] = "s";
assign ascii[4] = "t";
assign ascii[5] = " ";
assign ascii[6] = "L";
assign ascii[7] = "a";
assign ascii[8] = "s";
assign ascii[9] = "t";
assign ascii[10] = "n";
assign ascii[11] = "a";
assign ascii[12] = "m";
assign ascii[13] = "e";
or(ascii[0], Q[13]);
or(ascii[1], Q[12]);
or(ascii[2], Q[11]);
or(ascii[3], Q[10]);
or(ascii[4], Q[9]);
or(ascii[5], Q[8]);
or(ascii[6], Q[7]);
or(ascii[7], Q[6]);
or(ascii[8], Q[5]);
or(ascii[9], Q[4]);
or(ascii[10], Q[3]);
or(ascii[11], Q[2]);
or(ascii[12], Q[1]);
or(ascii[13], Q[0]);
endmodule
module RippleMod(CLK, Q);
input CLK;
output [0:15]Q;
reg [0:15]Q;
always #(posedge CLK) begin
Q[0] <= Q[15];
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
Q[4] <= Q[3];
Q[5] <= Q[4];
Q[6] <= Q[5];
Q[7] <= Q[6];
Q[8] <= Q[7];
Q[9] <= Q[8];
Q[10] <= Q[9];
Q[11] <= Q[10];
Q[12] <= Q[11];
Q[13] <= Q[12];
Q[14] <= Q[13];
Q[15] <= Q[14];
end
initial begin
Q[0] = 1;
Q[1] = 0;
Q[2] = 0;
Q[3] = 0;
Q[4] = 0;
Q[5] = 0;
Q[6] = 0;
Q[7] = 0;
Q[8] = 0;
Q[9] = 0;
Q[10] = 0;
Q[11] = 0;
Q[12] = 0;
Q[13] = 0;
Q[14] = 0;
Q[15] = 0;
end
endmodule
There are actually multiple issues with your program. i.e. you declare an ascii arraya as wire [6:0] ascii; but later you connect it to the module as CoderMod my_coder(Q, ascii); where it is an output port of width 14. You also assig 8-bit characters to a one-bit ascii, like here: ascii[1] = "i";
as a hint, you need to declare it as
wire [6:0] ascii [13:0];
you shold be able to figure out the rest.
I'm newbie to a verilog.
I did a lot of research, and finally wrote this code, but it seems to not work.
Can anyone fix it for me?
module comparator();
reg[3:0] a, b;
wire[1:0] equal, lower, greater;
if (a<b) begin
equal = 0;
lower = 1;
greater = 0;
end
else if (a==b) begin
equal = 1;
lower = 0;
greater = 0;
end
else begin
equal = 0;
lower = 0;
greater = 1;
end;
initial begin
$monitor($time,
"a=%b, b=%b, greater=%b, equals=%b, lower=%b",
a, b, greater, equal, lower);
a=9; b=10;
#100 $display ("\n", $time, "\n");
end
endmodule
Behavioural procedures must be enclosed within an always block, like this:
Also, your module needs inputs and outputs. A more correct version would be like this:
module comparator (
input wire [3:0] a,
input wire [3:0] b,
output reg equal,
output reg lower,
output reg greater
);
always #* begin
if (a<b) begin
equal = 0;
lower = 1;
greater = 0;
end
else if (a==b) begin
equal = 1;
lower = 0;
greater = 0;
end
else begin
equal = 0;
lower = 0;
greater = 1;
end
end
endmodule
I suggest reading some tutorial about behavioral modelling with Verilog, because you missed a lot of points:
How to correctly define inputs and outputs in a module
What things can be wires and what things should be regs
The use of always #* to model combinational logic
And most important: how to write a test bench. Test benches are written as module with no inputs and outputs) that instantiates your UUT (unit under test), provides inputs, read outputs and check whether they are valid.
module testcomp;
reg [3:0] a, b;
wire eq, lw, gr;
comparator uut (
.a(a),
.b(b),
.equal(eq),
.lower(lw),
.greater(gr)
);
initial begin
a = 0;
repeat (16) begin
b = 0;
repeat (16) begin
#10;
$display ("TESTING %d and %d yields eq=%d lw=%d gr=%d", a, b, eq, lw, gr);
if (a==b && eq!=1'b1 && gr!=1'b0 && lw!=1'b0) begin
$display ("ERROR!");
$finish;
end
if (a>b && eq!=1'b0 && gr!=1'b1 && lw!=1'b0) begin
$display ("ERROR!");
$finish;
end
if (a<b && eq!=1'b1 && gr!=1'b0 && lw!=1'b1) begin
$display ("ERROR!");
$finish;
end
b = b + 1;
end
a = a + 1;
end
$display ("PASSED!");
$finish;
end
endmodule
You can play with this example at EDAPlayGround using this link:
http://www.edaplayground.com/x/CPq
Without always block:
module comparator (
input wire [3:0] a,
input wire [3:0] b,
output reg equal,
output reg lower,
output reg greater
);
assign equal = (a===b);
assign lower = (a<b)?1'b1:1'b0;
assign greater = (a>b)1'b1:1'b0;
end
Be careful, you need to consider 'X' and 'Z', use "===" instead of "=="
I have a homework problem where I'm supposed to create a module for single-precision IEEE-754 floating point multiplication. This is the module:
module prob3(a, b, s);
input [31:0] a, b; // operands
output reg [31:0] s; // sum - Could potentially use wire instead
integer i; // loop variable
reg [8:0] temp;
reg [47:0] intProd; // intermediate product
reg [23:0] tempA;
reg [23:0] tempB;
initial begin
//Initialization
for (i = 0; i < 48; i = i + 1) begin
intProd[i] = 0;
end
//Compute the sign for the result
if (a[31]^b[31] == 0) begin
s[31] = 0;
end
else begin
s[31] = 1;
end
//Compute the exponent for the result
#10 temp = a[30:23] + b[30:23] - 8'b11111111;
//Case for overflow
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
//Case for underflow
else if (temp < 8'b00000001) begin
for (i = 0; i < 31; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else begin
s[30:23] = temp[7:0];
end
//Mutliply the signficands
//Make implicit one explicit
tempA[23] = 1;
tempB[23] = 1;
//Make operands 24 bits
for(i = 0; i < 23; i = i + 1) begin
tempA[i] = a[i];
tempB[i] = b[i];
end
//Compute product of signficands
intProd = tempA * tempB;
//Check and see if we need to normalize
if(intProd[47:46] >= 2'b10) begin
intProd = intProd >> 1;
temp = s[30:23] + 1'b1;
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else
s[30:23] = temp[7:0];
end
s[22:0] = intProd[47:25];
end
endmodule
Here is my testbench:
module prob4;
reg [31:0] a, b;
wire [31:0] s;
// instantiate the floating point multiplier
prob3 f1(a, b, s);
initial begin
assign a = 32'h42055555;
assign b = 32'hBDCCCCCD;
#10 $monitor("s = %h", s);
assign a = 32'hBF555555;
assign b = 32'hCAB71B00;
#10 $monitor("s = %h", s);
a = 32'hFF500000;
b = 32'h7E700000;
#10 $display("s = %b", s);
a = 32'h01700000;
b = 32'h02F00000;
#10 $display("s = %b", s);
a = 32'hBE000000;
b = 32'h455F36DB;
#10 $display("s = %b", s);
a = 32'h3C800000;
b = 32'h3A800000;
#10 $display("s = %b", s);
a = 32'hC797E880;
b = 32'hB7FBA927;
#10 $display("s = %b", s);
end
endmodule
It displays the first value of s, but that is it. I'm honestly not too familiar with Verilog, so any clarification on why this might be happening would be truly appreciated.
The reason you are seeing only a single value for s is because all of your floating point logic (all the stuff in the prob3 module) is inside an initial block. Thus, you only run that code once; it starts at time 0, has a pause for 10 time units and finishes; never to run again. Here are a few tips for implementing the unit (assuming the module is suppose to be synthesizable and not just a functional verification model):
Place your combinational logic in an always #(*) block, not an initial block.
As toolic mentioned, only call $monitor once, and it will inform you whenever s or any other variables given as arguments change; thus you do not need the $display statements either unless you want to know the value of s at that point of execution (whether it changed or not and inline with the processes, so not necessarily the final value either). So typically your testbench main stimulus initial block would have $monitor() as the first line.
Don't call $finish inside your logic; ideally, you should set an error signal instead that the testbench might then choose to call $finish if it sees that error signal asserted.
Don't use assign inside procedural blocks (always, initial, etc), just say a = ... not assign a = ...