Why do I get a syntax error for omitting a semicolon after one #10, but it is not needed for others? [duplicate] - verilog

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Difference between #(posedge Clk); a<= 1'b1; and #(posedge Clk) a<= 1'b1;
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My friend wrote an FSM code that generates 3 numbers (1,4,1) in binary.
The code works and compiles in modelsim.
I wrote a testbench for it so I can simulate it.
The testbench code errors in line 24 and says this:
** Error: (vlog-13069) C:/Users/******/*****/fsm/fsm_tb.v(24): near "end": syntax error, unexpected end.
Which indicates that end is unexpected after the previous line #10. So maybe there is a semicolon missing, but I don't have semicolons in the other lines #10 either, so I do not understand the problem.
This is the actual FSM code
module fsm_detector (
input wire clk,
input wire in,
output wire out
);
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8, s9 = 9, s10 = 10;
reg [3:0] state, next_state;
always #(posedge clk) begin
state <= next_state;
end
always #* begin
case (state)
s0: begin
if (in == 1'b0) next_state = s1;
else next_state = s0;
end
s1: begin
if (in == 1'b0) next_state = s2;
else next_state = s0;
end
s2: begin
if (in == 1'b0) next_state = s3;
else next_state = s0;
end
s3: begin
if (in == 1'b1) next_state = s4;
else next_state = s0;
end
s4: begin
if (in == 1'b0) next_state = s5;
else next_state = s0;
end
s5: begin
if (in == 1'b1) next_state = s6;
else next_state = s0;
end
s6: begin
if (in == 1'b0) next_state = s7;
else next_state = s0;
end
s7: begin
if (in == 1'b0) next_state = s8;
else next_state = s0;
end
s8: begin
if (in == 1'b0) next_state = s9;
else next_state = s0;
end
s9: begin
if (in == 1'b0) next_state = s10;
else next_state = s0;
end
s10: begin
if (in == 1'b1) next_state = s0;
else next_state = s0;
end
endcase
end
assign out = (state == s10);
endmodule
This is the test bench I wrote:
`timescale 1ns / 1ps
module fsm_detector_tb;
reg clk;
reg in;
wire out;
fsm_detector dut (
.clk(clk),
.in(in),
.out(out)
);
// Initialize input and output signals
initial begin
clk = 0;
in = 0;
#10
clk = 1;
#10
clk = 0;
#10
end
// Stimulus for detecting "000101000001" sequence
initial begin
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b1;
#20 in = 1'b0;
#20 in = 1'b1;
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b0;
#20 in = 1'b1;
end
endmodule
How can I fix this?

Answer 1

The problem is in this testbench initial block:
initial begin
clk = 0;
in = 0;
#10
clk = 1;
#10
clk = 0;
#10
end
The fix is to add a semicolon after the last #10:
initial begin
clk = 0;
in = 0;
#10
clk = 1;
#10
clk = 0;
#10;
end
All statements must end with a semicolon. What is tricky about your code is that the 1st 2 times you use #10, you don't need the semicolon.
The compiler parsers the code like:
initial begin
clk = 0;
in = 0;
#10 clk = 1;
#10 clk = 0;
#10
end
The #10 clk = 1; is the complete statement.
Also, you could use a semicolon after all 3 #10:
initial begin
clk = 0;
in = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
end