So i am currently doing a little project involving a hd44780 display. But since i want to write my own init sequence i decided to use a state machine. I am quite new to FPGAs an their programming coming from a Java background.
This is my State machine Block.
I this state it works and the IDE doesnt show any errors.
always #(posedge reset)
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
if(timeout == 0)
begin //Begin of Initiation state machine
case(state)
s0:
begin
end
s1:
begin
end
s2:
begin
end
s3:
begin
end
s4:
begin
end
s5:
begin
end
s6:
begin
end
s7:
begin
end
s8:
begin
end
s9:
begin
end
s10:
begin
end
normal:
begin
end
endcase
end //End of Initiation state machine
But if i add any assignment between the begin and end of one of the states it shows me "Line n: Syntax error near "<="."
for example:
case(state)
s0:
begin
state <= s1;
end
Full code of my DisplayDriver so far:
module DisplayDriver(
output reg [8:0] data,
output reg en,
output reg rs,
output reg rw,
output reg debug,
input clk,
input reset
);
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,normal = 11;
reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal
reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal [next State]
reg [1:0] en_timeout; // 2 bit for en high to low to high cylce
reg [13:0] timeout; // 14 bit
initial
// begin init
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
// end of init
always #(posedge clk)
//begin of everything that needs the clock
begin
if(en_timeout > 0) //begin timeout stack
begin
en_timeout <= en_timeout -1;
en <= ~en;// if en_timeout = 2 -> en = 0; if en_timeout = 1 -> en = 1;
end
else if (timeout > 0) timeout <= timeout -1; //end timeout stack
if(timeout == 0)state <= next_state;
end //end of everything that needs the clock
always #(posedge reset)
begin
en_timeout <= 2'b00;
timeout <= 14'b00000000000000;
init <= 4'b000;
data <= 8'b00000000;
en <= 1'b1; //active low
rs <= 1'b0;
rw <= 1'b0;
state <= 4'b0000;
next_state <= 4'b0000;
debug <= 1'b0;
end
if(timeout == 0)
begin //Begin of Initiation state machine
case(state)
s0:
begin
end
s1:
begin
end
s2:
begin
end
s3:
begin
end
s4:
begin
end
s5:
begin
end
s6:
begin
end
s7:
begin
end
s8:
begin
end
s9:
begin
end
s10:
begin
end
normal:
begin
end
endcase
end //End of Initiation state machine
endmodule
Does anyone have an idea why it behaves this way?
I assume that you are trying to synthesize a register for "state", in which case the update "<=" needs to be inside always (#posedge clk).
Related
I am trying to write a Finite State Machine for an assignment. However, I don't understand what is wrong with my module code. I get the error:
ERROR VCP5221 "Illegal reference to memory: st." "design.sv" 77 5
when I try to synthesize. I think I've either misunderstood how switch-case is used in Verilog or I've attempted to make an illegal assignment inside the switch-case but I don't know how to find it.
//Code here
module MooreFSM(
input clk,
input in,
output out
);
reg state[2:0];
reg sel[2:0];
reg o;
assign out = o;
initial begin
state <= 3'b000;
o <= 1'b0;
end
always#(negedge clk) begin
state <= sel;
end
always#(posedge clk) begin
case(state)
3'b000: begin
if(in == 1'b0) begin
sel <= 3'b010;
o <= 1'b0;
end
else if(in == 1'b1) begin
sel <= 3'b001;
o <= 1'b0;
end
end
3'b001: begin
if(in == 1'b0) begin
sel <= 3'b000;
o <= 1'b0;
end
else if(in == 1'b1) begin
state <= 3'b011;
o <= 1'b0;
end
end
3'b010: begin
if(in == 1'b0) begin
sel <= 3'b100;
o <= 1'b0;
end
else if(in == 1'b1) begin
sel <= 3'b000;
o <= 1'b0;
end
end
3'b011: begin
if(in == 1'b0) begin
sel <= 3'b000;
o <= 1'b1;
end
else if(in == 1'b1) begin
sel <= 3'b011;
o <= 1'b1;
end
end
3'b100: begin
if(in == 1'b0) begin
sel <= 3'b100;
o <= 1'b1;
end
else if(in == 1'b1) begin
sel <= 3'b000;
o <= 1'b1;
end
end
default: begin
sel <= 3'b000;
o <= 1'b0;
end
endcase
end
endmodule
Please help me identify the problem, or if I need to use a different method to synthesize a mux.
I think when you put
else if(in == 1'b1) begin
state <= 3'b011;
o <= 1'b0;
end
you might have meant to write
else if(in == 1'b1) begin
sel <= 3'b011;
o <= 1'b0;
end
By putting state as something being assigned in just one case of this switch statement, you're implicitly asking for it to be latched back to in every other case, which conflicts with you explicitly making it a flop above.
I have the main module with FIFO stuff.
Here it is:
module syn_fifo #(
parameter DATA_WIDTH = 8, // inpit capacity
parameter DATA_DEPTH = 8 // the depth of the FIFO
)
(
input wire clk,
input wire rst,
// Write_______________________________________________
input wire [DATA_WIDTH-1:0]din, // the input data
input wire wren, // Write anable
output wire full,
// Read________________________________________________
output wire [DATA_WIDTH-1:0]dout, // The output data
input wire rden, // Read enable
output wire empty
);
integer q_size; // The queue size(length)
integer golova; // The queue beginning
integer hvost; // The end of queue
reg [DATA_WIDTH-1:0]fifo[DATA_DEPTH-1:0];
assign full = (q_size == DATA_DEPTH) ? 1'b1: 1'b0; // FIFO is full
/*
True { full = (q_size==DATA_TEPTH) = 1 }, then wire "full" goes to "1" value
False { full = (q_size==DATA_TEPTH) = 0 }, then wire "full" goes to "0" value
*/
assign empty = (golova == hvost); // FIFO is empty
assign dout = fifo[hvost]; // FWFT (other write mode)
integer i;
//___________(The queue fullness)___________________
always #(posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
for (i = 0; i < DATA_DEPTH; i = i + 1) // incrementing the FIFO
fifo[i] <= 0; // Resetting the FIFO
golova <= 0; // Resetting the queue start variable
end
else
begin //Write_______________________________________
if (wren && ~full)
begin
fifo[golova] <= din; // putting data in to the golova
if (golova == DATA_DEPTH-1) // restrictions for the queue beginning
golova <= 0; // Reset the beginning
else
golova <= golova + 1; // other occurence incrementing
end
end
end
//Reading
always #(posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
hvost <= 0;
end
else
begin
if (rden && !empty)
/*for staying inside the queue limits - make the check of non equality of the "hvost" & "queue size"*/
begin
if (hvost == DATA_DEPTH-1) // if hvost = DATA_DEPTH-1, then
hvost <= 0; // Reset hvost
else
hvost <= hvost + 1;
end
end
end
always # (posedge clk)
begin
if (rst == 1'b1) begin
q_size <= 0;
end
else
begin
case ({wren && ~full, rden && ~empty} )
2'b01: q_size <= q_size + 1; // RO
2'b10: q_size <= q_size - 1; // WO
default: q_size <= q_size; // read and write at the same time
endcase
end
end
endmodule
Also i've got the testbench module down delow:
`timescale 1ns / 1ps
module fifo_tb();
localparam CLK_PERIOD = 10;
reg clk;
reg rst;
always begin
clk <= 1'b0;
#(CLK_PERIOD / 2);
clk <= 1'b1;
#(CLK_PERIOD / 2);
end
localparam DATA_WIDTH = 8;
localparam DATA_DEPTH = 4;
reg [DATA_WIDTH-1:0]din;
reg wren;
reg rden;
wire [DATA_WIDTH-1:0]dout;
wire empty;
wire full;
wire wr_valid;
wire rd_valid;
task write;
input integer length;
begin
if (length) begin
#(posedge clk);
wren <= 1'b1;
while (length) begin
#(posedge clk);
if (wr_valid) begin
length <= length - 1;
if (length == 1) begin
wren <= 1'b0;
end
end
end
end
end
endtask
task read;
input integer length;
begin
if (length) begin
#(posedge clk);
rden <= 1'b1;
while (length) begin
#(posedge clk);
if (rd_valid) begin
length <= length - 1;
if (length == 1) begin
rden <= 1'b0;
end
end
end
end
end
endtask
initial begin
rst <= 1'b0;
wren <= 1'b0;
rden <= 1'b0;
#50;
rst <= 1'b1;
#50;
rst <= 1'b0;
#200;
/* Test Start */
//write(4);
//read(4);
/* Test Stop */
#1000;
$finish;
end
assign wr_valid = wren & ~full;
assign rd_valid = rden & ~empty;
always #(posedge clk) begin
if (rst == 1'b1) begin
din <= 0;
end else begin
if (wr_valid == 1'b1) begin
din <= din + 1;
end
end
end
// write?
always begin
#400;
write(5);
#15;
write(7);
#25;
write(3);
#15;
write(9);
#15;
write(1);
#10000;
end
// read?
always begin
#420;
read(3);
#37;
read(13);
#21;
read(7);
#15;
read(9);
#15;
read(4);
#20;
read(7);
#10000;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0,fifo_tb);
end
syn_fifo #(.DATA_WIDTH(DATA_WIDTH),
.DATA_DEPTH(DATA_DEPTH)) dut ( .clk(clk),
.rst(rst),
.din(din),
.wren(wren),
.full(full),
.dout(dout),
.rden(rden),
.empty(empty));
endmodule
Trying to compile all of it with iVerilog + GTKwave + Win10 by next command:
C:\Program Files\iverilog\bin>iverilog -o fifo.v fifo_tb.v
The compiler gives me the next message:
fifo_tb.v:138:error: Unknown module type:syn_fifo
2 error(s) during elaboration.
These modules were missing:syn_fifo referenced 1 times
At the necessary line "138" maybe the main mistake is covered by the "Number sign" in module instantiation?
/*132|*/ initial begin
/*133|*/ $dumpfile("test.vcd");
/*134|*/ $dumpvars(0,fifo_tb);
/*135|*/ end
/*136|*/
/*137|*/ syn_fifo #(.DATA_WIDTH(DATA_WIDTH),
/*138|*/ .DATA_DEPTH(DATA_DEPTH)) dut ( .clk(clk),
/*139|*/ .rst(rst),
/*140|*/ .din(din),
/*141|*/ .wren(wren),
/*142|*/ .full(full),
/*143|*/ .dout(dout),
/*144|*/ .rden(rden),
/*145|*/ .empty(empty));
/*146|*/
/*147|*/ endmodule
I'm not shure of that.
Seems like you are indicating fifo.v to be your output file, try:
iverilog -o syn_fifo.tb -s fifo_tb fifo_tb.v fifo.v
-o -> output file
-s -> top module (in this case, the test one)
(after everything, include all the files)
Then, to run it:
vvp syn_fifo.tb
Thank you, dear #m4j0rt0m
I just forgot to type in the output file name at the CMD window. Was very exhausted so haven't noticed such a detail)))
Usually it looks like:
iverilog -o OUTPUT_FILE_NAME fifo_tb.v fifo.v
And also I tried your advice, and it's finally done!
Verilog Error
I am trying to learn verilog . This code is made for seven segment led using counter. But I am not able to assign value to nr it gives error. I made a state machine and wish to get next number on seven segment led after each positive clock.
/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/
module LED ( nr,clk);
input clk;
output [6:0]nr; //output led seven bit number
reg [6:0]nr;
reg [2:0]state;
always #(posedge clk);
begin
state <= 3'b000; // assigning at each clock
case (state)
3'b000:
begin
nr <= 7'b0000001;
state <= 3'b001;
end
3'b001:
begin
nr <= 7'b0011111;
state <= 3'b010;
end
3'b010:
begin
nr <= 7'b0100101;
state <= 3'b011;
end
3'b011:
begin
nr <= 7'b0001100;
state <= 3'b100;
end
3'b100:
begin
nr <= 7'b1011010;
state <= 3'b101;
end
3'b101:
begin
nr <= 7'b1001000;
state <= 3'b110;
end
3'b110:
begin
nr <= 7'b1000000;
state <= 3'b111;
end
3'b111:
begin
nr <= 7'b0011101;
state <= 3'b000;
end
end
endmodule
always #(posedge clk) no semicolon!
I having been trying to implement a simple sequence detector on a Nexys 3 (Spartan 6) board. The code works perfectly on Xilinx simulation but on the hardware, it doesn't work. Since I am new to FPGA implementation I couldn't solve this issue.
I dont know what changes I should make for the code to work in hardware.
It would be great if someone could help me..
And this is the code
module sequence( in, clock,reset,test);
input in;
input reset;
output reg test=0;
reg [3:0] state=0, next=0 ;
input clock;
always#( posedge clock)
begin
if(reset==1)
begin
state= 0;
end
else
begin
state=next;
end
end
always #*
begin
if(reset == 1)
begin
next=0;
test=0;
end
else
begin
case ( state )
'd0 : begin
if ( in==1)
begin
next=state+1;
end
else
next=next;
end
'd1 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd2 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd3 : begin
if ( in==1)
begin
next=state+1;
end
else
next=0;
end
'd4 : begin
if ( in==1)
begin
next=state+1;
test=1;
end
else
next=0;
end
default : begin
next=0;
test=0;
end
endcase
end
end
endmodule
I would change the beginning of your always block to:
always #*
begin
next = state;
test = 0;
case (state)
'd0 :
begin
if ( in==1)
next=state+1;
end
...
Setting a default assignment to all values in the state machine eliminates the possibility of creating an implicit latch. Your "next = next" statement shouldn't have any effect but might be creating latch (should probably be "next = state').
Also test is not assigned in every branch and has no default, so it will also create a latch.
The problems that I found in your Verilog code is given below.
Output variable test must be assigned in every case statement branches, else unwanted latches will form.
Use nonblocking assignments when you are specifying sequential circuit.
Try to code your sequence detector as below.
//sequence detector 101101
module fsm (rst,in1,clk,out1);
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
input rst,in1,clk;
output reg out1;
reg [2:0] state;
always #(posedge clk)
if (rst)
begin
state <= s0;
out1 <= 0 ;
end
else
case(state)
s0 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s1 : if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s2 : if (in1) begin state <= s3; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s3 : if (in1) begin state <= s4; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s4 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s5; out1 <= 0 ; end
s5 : if (in1) begin state <= s1; out1 <= 1 ; end
else begin state <= s0; out1 <= 0 ; end
default: if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
endcase
endmodule
I have a program written in Verilog and I want to convert it into a FSM automatically. Is this possible (just to visualize it)?
Here is the code :
module pci(reset,clk,frame,irdy,trdy,devsel,idsel,ad,cbe,par,stop,inta,led_out);
input reset;
input clk;
input frame;
input irdy;
output trdy;
output devsel;
input idsel;
inout [31:0] ad;
input [3:0] cbe;
inout par;
output stop;
output inta;
output [3:0] led_out;
parameter DEVICE_ID = 16'h9500;
parameter VENDOR_ID = 16'h106d; // Sequent!
parameter DEVICE_CLASS = 24'hFF0000; // Misc
parameter DEVICE_REV = 8'h01;
parameter SUBSYSTEM_ID = 16'h0001; // Card identifier
parameter SUBSYSTEM_VENDOR_ID = 16'hBEBE; // Card identifier
parameter DEVSEL_TIMING = 2'b00; // Fast!
reg [2:0] state;
reg [31:0] data;
reg [1:0] enable;
parameter EN_NONE = 0;
parameter EN_RD = 1;
parameter EN_WR = 2;
parameter EN_TR = 3;
reg memen; // respond to baseaddr?
reg [7:0] baseaddr;
reg [5:0] address;
parameter ST_IDLE = 3'b000;
parameter ST_BUSY = 3'b010;
parameter ST_MEMREAD = 3'b100;
parameter ST_MEMWRITE = 3'b101;
parameter ST_CFGREAD = 3'b110;
parameter ST_CFGWRITE = 3'b111;
parameter MEMREAD = 4'b0110;
parameter MEMWRITE = 4'b0111;
parameter CFGREAD = 4'b1010;
parameter CFGWRITE = 4'b1011;
`define LED
`ifdef LED
reg [3:0] led;
`endif
`undef STATE_DEBUG_LED
`ifdef STATE_DEBUG_LED
assign led_out = ~state;
`else
`ifdef LED
assign led_out = ~led; // board is wired for active low LEDs
`endif
`endif
assign ad = (enable == EN_RD) ? data : 32'bZ;
assign trdy = (enable == EN_NONE) ? 'bZ : (enable == EN_TR ? 1 : 0);
assign par = (enable == EN_RD) ? 0 : 'bZ;
reg devsel;
assign stop = 1'bZ;
assign inta = 1'bZ;
wire cfg_hit = ((cbe == CFGREAD || cbe == CFGWRITE) && idsel && ad[1:0] == 2'b00);
wire addr_hit = ((cbe == MEMREAD || cbe == MEMWRITE) && memen && ad[31:12] == {12'b0, baseaddr});
wire hit = cfg_hit | addr_hit;
always #(posedge clk)
begin
if (~reset) begin
state <= ST_IDLE;
enable <= EN_NONE;
baseaddr <= 0;
devsel <= 'bZ;
memen <= 0;
`ifdef LED
led <= 0;
`endif
end
else begin
case (state)
ST_IDLE: begin
enable <= EN_NONE;
devsel <= 'bZ;
if (~frame) begin
address <= ad[7:2];
if (hit) begin
state <= {1'b1, cbe[3], cbe[0]};
devsel <= 0;
// pipeline the write enable
if (cbe[0])
enable <= EN_WR;
end
else begin
state <= ST_BUSY;
enable <= EN_NONE;
end
end
end
ST_BUSY: begin
devsel <= 'bZ;
enable <= EN_NONE;
if (frame)
state <= ST_IDLE;
end
ST_CFGREAD: begin
enable <= EN_RD;
if (~irdy || trdy) begin
case (address)
0: data <= { DEVICE_ID, VENDOR_ID };
1: data <= { 5'b0, DEVSEL_TIMING, 9'b0, 14'b0, memen, 1'b0};
2: data <= { DEVICE_CLASS, DEVICE_REV };
4: data <= { 12'b0, baseaddr, 8'b0, 4'b0010 }; // baseaddr + request mem < 1Mbyte
11: data <= {SUBSYSTEM_ID, SUBSYSTEM_VENDOR_ID };
16: data <= { 24'b0, baseaddr };
default: data <= 'h00000000;
endcase
address <= address + 1;
end
if (frame && ~irdy && ~trdy) begin
devsel <= 1;
state <= ST_IDLE;
enable <= EN_TR;
end
end
ST_CFGWRITE: begin
enable <= EN_WR;
if (~irdy) begin
case (address)
4: baseaddr <= ad[19:12]; // XXX examine cbe
1: memen <= ad[1];
default: ;
endcase
address <= address + 1;
if (frame) begin
devsel <= 1;
state <= ST_IDLE;
enable <= EN_TR;
end
end
end
ST_MEMREAD: begin
enable <= EN_RD;
if (~irdy || trdy) begin
case (address)
`ifdef LED
0: data <= { 28'b0, led };
`endif
default: data <= 'h00000000;
endcase
address <= address + 1;
end
if (frame && ~irdy && ~trdy) begin
devsel <= 1;
state <= ST_IDLE;
enable <= EN_TR;
end
end
ST_MEMWRITE: begin
enable <= EN_WR;
if (~irdy) begin
case (address)
`ifdef LED
0: led <= ad[3:0];
`endif
default: ;
endcase
address <= address + 1;
if (frame) begin
devsel <= 1;
state <= ST_IDLE;
enable <= EN_TR;
end
end
end
endcase
end
end
endmodule
If there is no automatic way, could you explain a way of doing this?
Here is an FSM made with hand but can't test so ...
Does it seem ok?
It is sometimes easier to write the code and have the documentation generated from that. Sometimes you inherit legacy code without documentation, in these situations especially if new to a language tools to help visualise what is happening can be quite useful.
With cadence tools you can run your code with 'code coverage' then imc can load the coverage data and run FSM Analysis.
I have included a simple FSM below and show the generated state diagram.
module simple_fsm();
//Inputs to FSM
logic clk;
logic rst_n;
logic [1:0] state ;
logic [1:0] nextstate;
logic turn_on ;
logic turn_off ;
localparam S_OFF = 2'b00;
localparam S_GO_ON = 2'b01;
localparam S_ON = 2'b10;
localparam S_GO_OFF = 2'b11;
// State FlipFlop
always #(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b0;
end
else begin
state <= nextstate;
end
end
//Nextstate Logic
always #* begin
case (state)
2'd0 : if (turn_on) begin
nextstate = S_GO_ON;
end
2'd1 : nextstate = S_ON;
2'd2 : if (turn_off) begin
nextstate = S_GO_OFF ;
end
2'd3 : nextstate = S_OFF;
endcase
end
//TB clk
initial begin
#1ns;
clk = 0;
forever begin
#20ns;
clk = ~clk;
end
end
//The Test
initial begin
rst_n = 1'b0;
turn_on = 1'b0;
turn_off = 1'b0;
#(posedge clk);
#(posedge clk);
rst_n = 1'b1 ;
#(posedge clk);
turn_on = 1'b1;
#(posedge clk);
turn_on = 1'b0;
#(posedge clk);
#(posedge clk);
#100ms;
$finish();
end
endmodule
Execute with :
$ irun simple_fsm.sv -coverage all -covdut simple_fsm
$ imc &
Load cov_work (folder created by above simulation) in imc, select simple_fsm and choose FSM Analysis.
imc also helps to visualise your test coverage as well. Arcs and states that have not been hit are shown in red.
We have seen that there are some tools which can visualise the FSM, another part of the question is; is the syntax of the purposed FSM suitable for these tools.
#vermaete has reported that Modelsim SE can not see the FSM. From imc I get :
Which does not seem to cover the complexity of the code, and is shown as only having 2 reachable states, IDLE and BUSY. I would recommend if OP is going down the route of using tools to visualise, adopt a simpler (syntax) FSM structure so that the tools can parse it better.
The better and expensive simulators can detect FSM's in the code and make a visualization of it. E.g. the Modelsim SE version. These can be nice to understand code and check the coveage.
But making you're own drawing of a 6-state FSM is not that hard.
The way to check if it's OK is to write a simulation and check that the behaviour is what you want. There is no point getting a bubble diagram out and seeing if it matches your hand-drawn one, as you have no way of knowing if your hand-drawn diagram is correct...
case(segmentRead)
//-------------------
SEGMENT0: begin
READ_Ready_EEPROM <= 1'b0;
READ_RDSR_Enable <= 1'b0;
Read_Enable <= 1'b0;
READ_RDSR_DATA_REG <= 8'b0;
// READ_DATA_REG <= 8'b0;
end
//-------------------
SEGMENT2: begin
READ_RDSR_Enable <= 1'b1;
READ_RDSR_DATA_REG <= 8'b0;
end
// //-------------------
SEGMENT3: begin
READ_RDSR_Enable <= 1'b0;
READ_RDSR_DATA_REG <= RDSR_Data;
end
//-------------------
SEGMENT4: begin
Read_Enable <= 1'b1;
end
//-------------------
SEGMENT5: begin
Read_Enable <= 1'b0;
READ_DATA_REG <= Read_Data;
end
//-------------------
SEGMENT6: begin
READ_Ready_EEPROM <= 1'b1;
end
//-------------------
endcase