Implementation of a TDC in System Verilog - verilog

Question

I'm attempting to implement a Time to Digital Converter (TDC) in System Verilog. So far I've attempted 2 different methods and not sure if either has been successful.
The First Method is based on the following diagram
'''
module TDC #(
parameter bits = 8
)(
input logic start,
input logic progate_stop,
input logic reset,
output logic [bits-1:0] comb_output
);
logic comb_one, comb_two, comb_three, comb_four, comb_five, comb_six, comb_seven, comb_eight;
logic pipo_one, pipo_two, pipo_three, pipo_four, pipo_five, pipo_six, pipo_seven, pipo_eight;
always_comb begin
comb_one = start;
comb_two = ~comb_one;
comb_three = ~comb_two;
comb_four = ~comb_three;
comb_five = ~comb_four;
comb_six = ~comb_five;
comb_seven = ~comb_six;
comb_eight = ~comb_seven;
end
always_ff#(progate_stop) begin
if (reset ) begin
pipo_one <= 1'b0;
pipo_two <= 1'b0;
pipo_three <= 1'b0;
pipo_four <= 1'b0;
pipo_five <= 1'b0;
pipo_six <= 1'b0;
pipo_seven <= 1'b0;
pipo_eight <= 1'b0;
end else begin
pipo_one <= comb_one;
pipo_two <= comb_two;
pipo_three <= comb_three;
pipo_four <= comb_four;
pipo_five <= comb_five;
pipo_six <= comb_six;
pipo_seven <= comb_seven;
pipo_eight <= comb_eight;
end
end
always_comb begin
comb_output[0] = pipo_one;
comb_output[1] = ~pipo_two;
comb_output[2] = pipo_three;
comb_output[3] = ~pipo_four;
comb_output[4] = pipo_five;
comb_output[5] = ~pipo_six;
comb_output[6] = pipo_seven;
comb_output[7] = ~pipo_eight;
end
endmodule
The second method is based on the following diagram:
module TDC (
output reg [7:0] out , // Output of the counter
input wire enable , // enable for counter
input wire clk , // clock Input
input wire reset, // reset Input
input logic start,
input logic stop
);
//-------------Code Starts Here-------
always_ff #(posedge clk) begin
if (reset) begin
out <= 8'b0 ;
end else begin
if (start && !stop) begin
out <= out+1;
end else begin
out <=out;
end
end
end
endmodule
Any advice on either of these would be greatly appreciated!
Thank you in advanc

Answer 1

a TDC is very dependant on the underlying technology that you are using. Although it is a "digital" block (in the sense that you use digital gates and flops to implement it), the reality is that in order to obtain accurate timings, you need to carefully lay out the gates and the flops, so typically you will need:
a) describe the circuit structurally, using the cells available in your ASIC library/FPGA
b) carefully lay out the elements so that TDC timing measurements are accurate.
In other words, writing behavioural RTL as you're doing is not going to achieve what you want, sorry.