I am trying to use `define to reduce the number of lines when coding with SystemVerilog. I can use it as below:
`define a(num) tb.a.b.c.d.mem[num];
But, I want to use as below:
`define a(num) tb.a.b.c.d.memnum;
The result should be as below:
`a(0) ===> tb.a.b.c.d.mem0;
`a(1) ===> tb.a.b.c.d.mem1;
`a(2) ===> tb.a.b.c.d.mem2;
I don't know how to generate as above. Can anybody help me?
In order to generate tokens in macros where there isn't a normal delimiter (things like spaces, ., parens, etc) as in your case, you can use the double tick to explicitly separate tokens in the macro:
`define a(num) tb.a.b.c.d.mem``num
Related
I want to name a module using a `define directive
It seems to work if I use a macro like :
`define module_rename(NAME,TAG) ``NAME``TAG
module `module_rename(foo,_A) (...);
but it fails (in quartus) if I do the following :
`define NAME foo
`define TAG _A
module `NAME`TAG (...);
Syntax Error near_A missing";"
Any idea what is wrong ?
Tx for your help
The SystemVerilog token pasting operator `` is only allowed in the body of a `define text macro, and that is the only place you can join text together to form a single identifier. The second example you wrote is seen as illegal syntax.
module foo _A;
Is their a possibility to access a node in the code using a define macro via string parameters
e.g.
module design
(
input logic signal_in_1_temp,
input logic signal_in_2_temp
);
endmodule
module tb_top;
parameter string signal_names[0:1] = {"in_1","in_2"};
i_design design(.signal_in_1_temp(0),.signal_in_2_temp(0));
`define IN_SIG(IN_NAME,VAL)\
force i_design.signal_\``IN_NAME\``_temp = VAL;
initial begin
\`IN_SIG(signal_name[0],1);
\`IN_SIG(signal_name[1],0);
end
endmodule
In the above the two inputs of the design would need to be accessed via a parameter list and then a macro ...
Compiling the above gives error .... I would want to know if we can access the nodes status or drive them based on the above means ..
The idea is to have a dynamic parameter list given and then to know the status of that list or drive them based on need....
Any suggestions ... please
No, you cannot use string names within the language to build identifier names. Verilog does have a C interface (called VPI) that allows you to access signals by signal name, but that comes at a performance cost which means the signal cannot have certain optimizations and must remain intact.
SystemVerilog has a bind construct that allows you to attach functionality to signals deep inside your design. I wrote a DVCon paper about it.
No, you cannot do it with strings, but you can do it with regular macro arguments.
here is a working example:
`define A(B) \
$display(sig_``B``_sig);
module top;
logic sig_x_sig, sig_hello_sig;
initial begin
`A(x)
`A(hello)
end
endmodule
do not use \ as in your code and do not use empty lines in macro definitions.
I would like to define a parameter MYTYPE using text macro, whose value is passed over by text macro, eg
`define MY_FEATURE(nam,def) parameter nam=def;
and then
`MY_FEATURE(MYTYPE, 1)
But the value is mixed by those who are defined by other text macros, eg
`MY_FEATURE(NEWTYPE, 2)
`MY_FEATURE(MYTYPE, NEWTYPE)
The latter case will not work unless the def in define MY_FEATURE is added with the directive dot.
I need to distinguish this two different cases and automatically expand the macro - only if it is defined, so I came up with this code but I got error.
`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) `ifdef def parameter nam=`def; `else parameter nam=2; `endif
module test;
`MY_FEATURE(MYTYPE,yea)
initial begin
$display("%d",MYTYPE);
end
endmodule
The above code works and gives a 1 as output. However if I write
`MY_FEATURE(MYTYPE,10)
since for other cases I need to assign an actual number to the parameter, then I will get
`ifdef without a macro name - ignored.
My desired result is MYTYPE is assigned as 10.
Is there any way to achieve this? Thanks.
Code can be found here
http://www.edaplayground.com/x/6Jha
I think you are overthinking it. `define creates an directive expression. When when you pass a directive as parameter to another directive you can pass it as `yea.
Here is an example:
`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) parameter nam=def;
module test;
`MY_FEATURE(MYTYPE,`yea)
`MY_FEATURE(MYTYPE2,10)
`MY_FEATURE(MYTYPE3,MYTYPE+MYTYPE2)
initial begin
$display("%d %d %d",MYTYPE, MYTYPE2, MYTYPE3); // displays: 1 10 11
end
endmodule
http://www.edaplayground.com/x/5Pgf
Verilog-AMS (superset of Verilog-A) is a language of its own, derived from Verilog (IEEE Std 1364); according the manual. This means your MY_FEATURE never creates new directives; it creates parameters. Directives and parameters are both treated as constants in simulation but act differently in compile. The `define/parameters relation in Verilog (and Verilog derived languages) is equivalent to C's #define/const relation. Unlike C, to access the value of a `define requires a ` prefix.
Neither directives or parameters cannot start with a numeric value. The first character must be an alpha or underscore (aka [a-zA-Z_]). There for 10 can never be a directives and even trying to use it is illegal syntax. There is noway for the compile to recover from an illegal syntax directive name. This is way I suggested passing `yea instead of yea.
If someone build you a nice model, then it should come with equally nice documentation or some way of getting support.
For reasons which cannot be avoided (requirements of Qsys), I have several Verilog modules which end up with many ports which would be far easier to work with if they were packed. To try and explain what I mean, here is an example:
module foo #(
COUNT = 4
) (
//Interface 0
input bar_0,
output deadbeef_0,
//Interface 1
input bar_1,
output deadbeef_1,
//Interface 2
input bar_2,
output deadbeef_2,
//Interface 3
input bar_3,
output deadbeef_3,
);
...
endmodule
Now normally one would just make two vectorised ports (e.g. input [COUNT-1:0] bar,), however Qsys cannot cope with this if the signals need to be fed onto different interfaces - you can only select an entire port, not just a bit of one.
As you can imagine, this gets very irritating if internally you need to access the ports in something like a generate loop, and is especially problematic if you have a module with interfaces that have 10 ports which have to be written out 16 times!
What I've been doing up until now would be to add a mapping into the module manually. Again and example to explain - continuing the example above, I'd have something like this in the body of the module:
wire [COUNT-1:0] bar;
wire [COUNT-1:0] deadbeef;
generate
if (COUNT > 0) begin
assign bar[0] = bar_0;
assign deadbeef_0 = deafbeef[0];
end else begin
assign deadbeef_0 = 1'b0; //Terminate!
end
if (COUNT > 1) begin
assign bar[1] = bar_1;
assign deadbeef_1 = deafbeef[1];
end else begin
assign deadbeef_1 = 1'b0; //Terminate!
end
...
endgenerate
// deadbeef[] and bar[] can now be used as arrays, woop.
Even just writing out a couple of the interfaces for only two signals in that example was incredibly tedious!
Every part of the programmer in me is screaming out to stop doing this and that there must be a better way. And that brings me to my question:
Is there a simple way of doing this?
Ideally I'd have some form of loop which generates these mappings for me, generating the signal names from a loop variable. But I'm not sure if this is even possible in Verilog.
Also, just to make things interesting, I have been using hexadecimal for ports to make things easier when writing it out, for example:
input bar_0,
input bar_1,
...
input bar_9,
input bar_a,
input bar_b,
...
Ideally the solution to this would also cope with names like that, but to be honest I could easily convert the names to decimal (bar_10) if it simplifies things.
In case you are wondering, this is made very easy in Qsys to link the interfaces to ports because Qsys uses TCL files to make the mapping. In TCL I can simply use a for loop and concatenate the loop variable to make the names.
I guess, in your case, macro can be used to solve your problem. So, everywhere, in your code, you can use bar as a vector, though it is not.
Define a macro like this :
`define bar(n) bar_``n``
`define deadbeef(n) deadbeef_``n``
You can use now bar as a vector like below:
`bar(0)
`deadbeef(0)
Let's say I have some define macro, and then some other wire that is defined.
What does it mean when I have them like this? Is it just meaning to take the 2 LSBs from the wire?
`define A_DEFINE 32
// *SOME CODE IN HERE*
output [`A_DEFINE-1:0] my_out_wire;
// *MORE CODE HERE*
I can't seem to find any explanation of this meaning.
The syntax `define A_DEFINE 32 declares a macro called A_DEFINE. A macro is a thing you can use for text replacement in your code.
The syntax `A_DEFINE means expand the A_DEFINE macro. This is essentially taking the value of A_DEFINE and copying in the place where the macro is expanded.
The preprocessor does this for you. In essence, you'll end up with:
// *SOME CODE IN HERE*
output [32-1:0] my_out_wire;
// *MORE CODE HERE*
Defines are handy if you need to have a configurable element in your code. This way if you have multiple signals that are supposed to be as wide, you just use the define. In case you need to change from 32 to 64, you just modify the define and that's it.
Also have a look at the SystemVerilog parameter. This might also be helpful.