module Calculator(out,a,b,op);
input [3:0] a,b;
input [1:0] op;
output [4:0] out;
reg [32:0] out;
initial
begin
case(op)
2'b00: out <= a+b;
2'b01: out <= a-b;
2'b10: out <= a*b;
2'b11: out <= a/b;
endcase
out = a+b;
end
endmodule
module test_Calci;
reg [3:0]a,b;
reg [1:0] op;
wire [32:0] out;
Calculator ca1 (out,a,b,op);
initial
begin
#40 a=32'b1; b=32'b1; op = 2'b00;
end
endmodule
The code is successfully compiling, but the expected output is not being displayed.
The initial block inside the Calculator module only executes once at time 0. At that time, the last statement which is executed (out = a+b) assigns out to the value X because a and b are X. out never gets assigned again.
You want out to be assigned every time any of the inputs change value. To do that, use an always block:
module Calculator(out,a,b,op);
input [3:0] a,b;
input [1:0] op;
output reg [32:0] out;
always #* begin
case(op)
2'b00: out = a+b;
2'b01: out = a-b;
2'b10: out = a*b;
2'b11: out = a/b;
endcase
end
endmodule
I made other changes to your code as well. For combinational logic, it is a good practice to use blocking assignments (=) instead of nonblocking (<=).
You should not have the assignment to out outside of the case statement since it will override the value assigned in the case.
You declare out with 2 different bit widths (5 and 33), which is a little strange. I merged them into one declaration.
Related
module calculator(state,U,V,X,X_1,multiplicant,multiplier,count);
input [1:0] state;
input [3:0] multiplicant,multiplier;
output reg [3:0] U,V,X;
output reg X_1;
output reg[2:0] count;
wire [7:0] ASR;
wire [4:0] CSR;
wire [3:0] sum, sub;
always # (state or count)
begin
U<=4'b0;
V<=4'b0;
X<=multiplier;
X_1<=1'b0;
count<=3'b0;
if(state==2'b01)
begin
case({X[0],X_1})
2'b00:
begin
{U,V}<=ASR;
{X,X_1}<=CSR;
end
2'b11:
begin
{U,V}<=ASR;
{X,X_1}<=CSR;
end
2'b01:
begin
U<=sum;
{U,V}<=ASR;
{X,X_1}<=CSR;
end
2'b10:
begin
U<=sub;
{U,V}<=ASR;
{X,X_1}<=CSR;
end
endcase
count <= count +1;
end
end
rca U0_rca4(.a(multiplicant),.b(U),.ci(1'b0),.s(sum));
rca U1_rca4(.a(U),.b(~multiplicant),.ci(1'b1),.s(sub));
ASR8 U2_ASR8({U,V},1'b1,ASR);
CSR5 U3_CSR5({X,X_1},1'b1,CSR);
endmodule
This is my code, the case 2'b01 and case 2'b10 doesn't work. Actually, shifting works well but adding rca's sum or sub to 'U' doesn't work. Why does it happen? I need explain. Or can I modify my code better? I have to make 4bit*4bit -> 8bit result multiplier
you have multiple issues with your code.
First of all there are no clocks. The case statement looks full and is a combinational logic, however 'counter <= counter + 1` is not a combinational logic and requires a flop.
you are using non-blocking assignments '<=' all over the places, making your model simulating not as expected in any case, and also probably causing glitches and races in simulation. Please review the chapter about use of blockling/non-blocking assignments.
Now for the cases 01 and 10 you have multiple assignments to the U variable:
2'b01:
begin
U<=sum; // << here is assighment #1
{U,V}<=ASR; // << here is assignment #2
{X,X_1}<=CSR;
end
So, you just overwrite it in the next assignment, therefore, sum (and sub in 10) do not take any effect.
I'm totally new to Verilog programming and I do not understand where to initialize reg variables?
Let's have a look at the following snippets:
Edit:
Warning at synthesize
module test (
output LED0
);
reg led = 1'b1;
assign LED0 = led;
endmodule
or
module test (
output LED0
);
reg led;
initial begin
reg led <= 1'b1;
end
assign LED0 = led;
endmodule
Give me: Using initial value of led since it is never assigned at the line: reg led = 1'b1;
Are reg types only assigned in always# block?
Another example:
module fourBitCounter
(input clk,
output [3:0]counter
);
wire clk;
initial begin
reg[3:0] counter = 4'b1;
end
always# (posedge clk) begin
if(counter > 15)
counter <= 0;
else
counter <= counter + 1;
end endmodule
Here the reg has an initial value of 0 but I've set it before to 1... What's wrong? Thank you!
Are reg types only assigned in always# block?
No, reg types can be assigned in always blocks and initial blocks (plus task and function but I'll skip them in the scope of this question)
For your fourBitCounter, the reg[3:0] counter declared in the initial block creates a local variable also called counter that is only accessible within the scope of the block it was created in. You need to remove the reg[3:0] in the initial block so that the assignment get applied the the intended counter. But it will still not work because you declared counter as an inferred wire type and always/initial blocks cannot assign wires.
counter was declared as an output of a 4-bit inferred wire (output [3:0] counter is synonyms to output wire [3:0] counter). Since counter is assigned in an always block and initial block it needs to be a reg type. Therefore it should be declared as output reg [3:0] counter.
Also, you declared clk as in input and as a local wire, it cannot be both. Ports can be accessed locally, there is no reason to re-declare them as local nets.
FYI: for a 4-bit value, 15+1 equals 0 because there is nothing to store the MSB.
module fourBitCounter (
input clk,
output reg [3:0] counter // 'output reg', not 'output'
);
//wire clk; // do not do this, clk is an input
initial begin
counter = 4'b1; // no 'reg' here
end
always #(posedge clk) begin
if(counter > 15) // this will never evaluate as true with counter declared as 4-bit
counter <= 0;
else
counter <= counter + 1;
end
endmodule
For Verilog, assign statements can only be applied on net types (e.g. wire). This is legal:
module test ( output LED0 ); // LED0 is an inferred wire
assign LED0 = 1'b1;
endmodule
This is illegal:
module test ( output reg LED0 ); // Explicit reg
assign LED0 = 1'b1; // illegal, assign on a reg
endmodule
From your first code sample:
reg led; // <-- This declares one register called "led"
initial begin
reg led <= 1'b1; // <-- This declares a *separate* register called "led"
end // which is only valid in the initial block
The same issue exists in your second sample; you're declaring a separate register in the initial block. Don't use the keywords reg or wire if you're just trying to assign a value.
module ocircuit (ooutp,s0,s1 ,clk,write,raddA,raddB,wadd,wdata);
output [3:0] ooutp;
input clk, write,s0,s1;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
reg [9:0] ooutp;
wire [3:0] dataA;
wire [3:0] dataB;
reg [9:0] inner;
regfile y (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);
always #(posedge clk) begin
if (s0==0) begin
assign inner = dataA [3:0]*dataB [3:0];
end
else begin
assign inner = ((dataA [3:0]*dataB [3:0])+inner [9:0]);
end
//inner=inner1;
ooutp =s1?inner [9:0]:10'd0;
end
endmodule
This is the code. regfile is a simple register file. In the testbench, s0 = 0 during the first cycle and s0 = 1.
For subsequent cycles, this code should return the value of A*B+C*D by using one adder and one multiplier. In the first cycle, when c0 = 0, the answer that is saved in inner (a register) is right but in the second cycle, when c0 = 1 the answer is wrong.
Por example: A=1; B=2; C=1; D=1;
First cycle: x=A*B=2
Second cycle (C*D)+x=5
I think there is something wrong with this statement
assign inner = ((dataA [3:0]*dataB [3:0])+inner [9:0]);
Any help or hint will be appreciated.
Although assign can be used from within an always block, I think you just wanted to store a value into inner depending upon the value of s0. To do that, use non-blocking assignments ( <= ).
Also, you can directly output to ooutp instead of saving the final result in inner, avoiding a possible glitch in the multiplexer you instantiate here:
ooutp =s1?inner [9:0]:10'd0;
Which, by the way, it should be outside the always block, in an assign line:
assign ooutp = s1? inner [9:0]:10'd0;
module ocircuit (ooutp,s0,s1 ,clk,write,raddA,raddB,wadd,wdata);
output [3:0] ooutp;
input clk, write,s0,s1;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
reg [9:0] ooutp;
wire [3:0] dataA;
wire [3:0] dataB;
reg [9:0] inner;
regfile y (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);
always #(posedge clk) begin
if (s0==0) begin
inner <= dataA [3:0]*dataB [3:0];
end
else begin
ooutp <= ((dataA [3:0]*dataB [3:0])+inner [9:0]);
end
end
endmodule
I sometimes find it useful to use blocking assignments for "local variables" inside clocked always blocks. This can help cut down on repeated code.
To avoid accidentally using the same variable in a different always block (which can be non-deterministic for simulation), I'd like to give it local scope. Is there a nice synthesizable way of doing this?
Something like:
module sum3(
input clk,
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
output reg [7:0] result,
output reg [7:0] result_p1);
begin :sum
reg [7:0] sum_temp; // local variable
always #(posedge clk) begin
sum_temp = in1 + in2 + in3;
result <= sum_temp;
result_p1 <= sum_temp + 1;
end
end
endmodule
(ModelSim seems to be okay with this, but Synplify doesn't seem to like it.)
I'm not sure of the semantics in plain Verilog, but according to the SystemVerilog LRM section 6.21:
Variable declarations shall precede any statements within a procedural block.
Therefore the following is legal syntax in SystemVerilog:
module sum3(
input clk,
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
output reg [7:0] result,
output reg [7:0] result_p1);
always #(posedge clk) begin : sum
reg [7:0] sum_temp; // local variable (scope limited to process)
sum_temp = in1 + in2 + in3;
result <= sum_temp;
result_p1 <= sum_temp + 1;
end
endmodule
Note that I have moved the variable declaration sum_temp into the process, thereby limiting the scope and removing the need for the named sum block. This compiles on Modelsim and Riviera (example on EDA Playground).
If your tool doesn't support this syntax, raise a bug!
The standard sythesizable way is to use a continuous assignment with a wire:
module sum3(
input clk,
input [7:0] in1,
input [7:0] in2,
input [7:0] in3,
output reg [7:0] result,
output reg [7:0] result_p1);
wire [7:0] sum_temp = in1 + in2 + in3;
always #(posedge clk) begin
result <= sum_temp;
result_p1 <= sum_temp + 1;
end
endmodule
Despite the common guideline, using blocking assignments inside clocked always blocks is ok, and sometime as you mentioned useful. See here: https://stackoverflow.com/a/4774450/1383356
Some tools however, may not support local variables defined inside a begin-end block.
Alternatively, you can try putting some or all of the the body of the always block in a task:
task SUM_TASK();
reg [7:0] sum_temp; // local variable
sum_temp = in1 + in2 + in3;
result <= sum_temp;
result_p1 <= sum_temp + 1;
endtask
always #(posedge clk) begin
SUM_TASK();
end
Verilog tasks can have access to global variables as well as local ones. Also, they can include non-blocking assignments.
I am having trouble putting this code together my main code is a state machine it adds 2 numbers together = sum then loads A to add A to sum(sum=a+sum) after clock is reached it then divides by n bit. I'm lost putting it together. In having Lots of trouble assigning outputs. what is legal and what is not am I able to set the regs equal to each other sometimes I feel like I can do that and some other times I cannot.if I use the module can the input be an output and vice versa I posted my whole code cause I wanted to get it to work. I think my device is correct but I need to create a test bench to tested.
module Adder (A1, B1, Cin,Q);
parameter n = 5;
output[n:0]Q;
reg [n:0]Q;
input [n:0] A1;
wire[n:0] A1;
input [n:0] B1;
wire [n:0] B1;
input Cin;
always #(A1 or B1 or Cin)
begin
Q = A1 +B1 + Cin;
end
endmodule
module ave(Clk,X,LA,DataA,Sum,Q);
parameter n=5;
input A,B,EB,Temp,DataA,DataB,Sum,Q;
input X;
reg A,B,Temp,Sum;
reg y,Y
wire
reg S1=3'b000;S2=3'b001;S3=3'b010;S4=3'b011;S5=3'b100;
always (Clk)
begin
case(y)
S1:
y=S2;
S2:
y=S3;
S3:
if (counter>0) y=S2;
else y=S4;
S4:
y=S4;
S5:
Done;
endcase
end
always (Clk)
begin
case
S1:
Counter=n; Temp=n; Sum=0;
S2:
A=X;
S3:
if (counter>0) B<=A+B;
else B<=B;
S4:
DataA=Temp;
DataB=Sum;
S5:
Done=1;
end
Adder add(A,Sum,Cin,Sum);
divider divid(Clk,1,1,1,1,DataA,DataB,1,1,Q,0);
endmodule
this is my divider plus the other modules:
module shiftlne(R,C,L,w,Clk,Q);
parameter n=8;
input [n-1:0]R;
input L,w,Clk,C;
output [n-1:0]Q;
reg [n-1:0]Q;
integer k;
always #(posedge Clk)
begin
if(L)begin
if(C)begin
Q<=R;end
else
begin
for (k=0;k<(n-1);k=(k+1))
Q[k+1]=Q[k];
Q[0]<=w;
end
end
end
endmodule
module downcounter (R,E,L,Clk,Q);
parameter n=8;
input[n-1:0]R;
input Clk,L,E;
output [n-1:0]Q;
reg[n-1:0]Q;
always #(posedge Clk)
begin if(L)
Q<=R;
else if(E)
Q<=(Q-1);
end
endmodule
module muxdff( D0, D1, Sel, Clk,Q);
input Clk,D0,D1,Sel;
wire D;
output Q;
reg Q;
assign D=Sel?D1:D0;
always # (posedge Clk)
begin
Q=D;
end
endmodule
module regne (R,Clk,Resetn,E,Q);
parameter n=8;
input [n-1:0]R;
input Clk,Resetn,E;
output [n-1:0]Q;
reg [n-1:0] Q;
always #(posedge Clk or negedge Resetn)
begin
if (Resetn==0)
Q<=0;
else if (E)
Q<=R;
end
endmodule
Are you stuck using Verilog-95 if not you can clean up the code style, if nothing else it helps spot the bugs easier.
NB: Uses spaces to indent your code, not tabs as they mess up the formatting when posting Q's and can look different to people review your code depending on how there editor is setup.
module Adder #(
parameter n = 5
)(
input [n:0] A1, //Inputs do not have to be declared as wires
input [n:0] B1,
input Cin,
output reg [n:0] Q;
);
//Auto sensitivity list with #* lowers chance of bugs
always #* begin
Q = A1 + B1 + Cin;
end
endmodule
Most languages, and I apply this to my verilog keep constants like parameters and localparam in UPPERCASE, everything else is lowercase.
Your shiftlne code be made more readable: readable code to me implies easier to spot the bugs and understand the design intention.
always #(posedge Clk) begin
if( L ) begin
if( C ) begin
Q <= R;
end
else begin
for (k=0;k<(n-1);k=(k+1))
Q[k+1] = Q[k]; //For loop only applies to this line
// should it not be Q[k+1] <= Q[k];
Q[0] <= w;
end
end
end
endmodule