I have two modules namely main.v and signal.v.
In main.v, I have a few lines of code that update 16 bit reg tx with a value corresponding to a square wave.
reg [1:0] counter;
reg [15:0] tx;
always #(posedge clk) begin
counter = counter + 1;
if (counter[1] == 1) begin
tx[15:0] <= 16'b1010101010101010;
else
tx[15:0] <= 16'b0000000000000000;
end
This works fine. Eventually, though, I want to move this signal over to another file signal.v, because the signal that I pass to tx will grow steadily more complicated. I ran into errors when I try to do this. Initially, I tried to move all the above code to the file signal.v. Then used a wire between the two files as shown.
module signal(clk, get_tx);
input clk;
output reg get_tx;
reg [1:0] counter;
always #(posedge clk) begin
counter = counter + 1;
if (counter[1] == 1) begin
get_tx[15:0] <= 16'b1010101010101010;
else
get_tx[15:0] <= 16'b0000000000000000;
end
Then in main.v, I tried to add
wire get_tx;
reg [15:0] tx;
signal my_signal(.clk(clk), .get_tx(get_tx));
always #( get_tx ) begin
tx <= get_tx;
end
Based on what I see in the output oscilloscope, this method isn't working, and I'm not certain why this is. The first case seems to work fine, so I don't know why it is failing when I move to the second case (the signals just look completely different).
I would appreciate any help/advice!
First of all will be better to understand your connections and simulate your code if you add full code with modules declarations. The problems are in the signal types. Try to change output to wire. As well you need to declare bus, not just 1 bit signal. And give an initial value to your counter (in other case it will do follow operation 'X' +1 which gives 'X' in result and your condition if (counter[1] == 1) will never be achieved).
module signal(clk, get_tx);
input clk;
output [15:0] get_tx;
reg [15:0] tx_out;
reg [1:0] counter = 2'd0;
always #(posedge clk) begin
counter = counter + 1;
if (counter[1] == 1)
tx_out[15:0] <= 16'b1010101010101010;
else
tx_out[15:0] <= 16'b0000000000000000;
end
assign get_tx = tx_out;
endmodule
Next error in upper module, there you also need to declare bus rather than just one bit wire [15:0] get_tx;. Try to fix this errors and your modules will work.
This might seem like a very naive question, but I have just started working with Verilog (I use Xilinx ISE, if that helps).
I am trying to implement a shift register that shifts input PI by the value specified in the shft port. When I include the shifting logic in the RTL file, the shifting does not work, but when I move the always block corresponding to shifting to the testbench, it works. Please help me with this!
module shift (PI, shft, clk, PO);
input [7:0] PI;
input clk;
input [7:0] shft;
output reg [13:0] PO;
reg [7:0] shft_reg;
always #(posedge clk) begin
if (shft_reg[0]||shft_reg[1]||shft_reg[2]||shft_reg[3]||shft_reg[4]||shft_reg[5]||shft_reg[6]||shft_reg[7]) begin
PO <= {PO, 0};
shft_reg <= shft_reg-1;
end
end
endmodule
module shift (
input wire clk;
input wire load; // load shift register from input
input wire [7:0] PI;
input wire [7:0] shft; // this might need less bits
output wire [13:0] PO;
);
reg [7:0] shft_reg;
reg [13:0] value;
assign PO = value; // PO follows value
always #(posedge clk) begin
if (load) begin // initialize shift register and counter
shft_reg <= shft;
value <= {6'b0,PI};
end
else if (shft_reg) begin // if counter not reached end...
shft_reg <= shft_reg - 1; // decrement, and
value <= {value[13:1],1'b0}; // shift left value 1 bit
end
end
end
endmodule
Recall that Verilog supports the >> and << operators. For non-constants many-bit operands, this may be a waste of multiplexers, though:
module shiftcomb (
input wire [7:0] PI; // this value is left shifted
input wire [2:0] shft; // 0 to 7 bits positions
output wire [14:0] PO; // and is outputted to PO
);
assign PO = PI<<shft; // this will generate 15 mutlplexers:
// each one with 8 inputs, 3 bit select,
// and 1 output.
endmodule
Note that || is a logical or and idealy should be used with logical statments such as (shft_reg[0] == 1'b1 ) || ( shft_reg[1] == 1'b1).
Your if statment is really bitwise ORing all of the bits ie
shft_reg[0] | shft_reg[1] | shft_reg[2] | ...
You can use the OR Reduction operator :
|shft_reg
Your supplied code had typo'd PI for PO.
always #(posedge clk) begin
if (|shft_reg) begin
PO <= {PI, 0}; //PI input
shft_reg <= shft_reg-1;
end
end
I' trying to store value from wire named 'in' into reg 'a'.
But, the problem is value of reg 'a' is showing 'xxxx' in simulator. However, value of wire 'in' is showing correctly.
My target is just to read value from input wire and store it into a register.
module test(
input [3:0] in,
output [3:0] out
);
reg [3:0] a;
initial
begin
a = in;
end
endmodule
The reason why the value of a is 'xxxx' in the simulation is probably that a is set to the value of in only a single time initially, and a may not yet have been set to any specific value at this time in the simulation.
Declaring a reg in Verilog does not necessarily mean that a hardware register is described by the code. That usually involves the use of a clock signal:
module test(
input clk,
input [3:0] in,
output [3:0] out
);
// this describes a register with input "in" and output "a"
reg [3:0] a;
always #(posedge clk) begin
a <= in;
end
// I assume you want "a" to be the output of the module
assign out = a;
endmodule
Here is a counter example where a reg is used to describe something which is not a register, but only a simple wire:
module not_a_register(
input in,
output out
);
reg a;
always #(in) begin
a <= in;
end
assign out = a;
endmodule
Also note that I have used the non-blocking assignment operator <= inside the always block, which is good practice when describing synchronous logic. You can read more about it here.
I am designing a shift register using hierarchical structural Verilog. I have designed a D flip flop and an 8 to 1 mux that uses 3 select inputs. I am trying to put them together to get the full shift register, but my output only gives "XXXX" regardless of the select inputs.
Flip Flop Code
module D_Flip_Flop(
input D,
input clk,
output Q, Q_bar
);
wire a,b,c,d;
nand(a,D,b);
nand(b,a,clk,d);
nand(c,a,d);
nand(d,c,clk);
nand(Q,d,Q_bar);
nand(Q_bar,b,Q);
endmodule
8 to 1 Mux
module Mux8to1(
input [2:0]S,
input A,B,C,D,E,F,G,H,
output Out
);
wire a,b,c,d,e,f,g,h;
and(a, A,~S[2],~S[1],~S[0]);
and(b, B,~S[2],~S[1],S[0]);
and(c, C,~S[2],S[1],~S[0]);
and(d, D,~S[2],S[1],S[0]);
and(e, E,S[2],~S[1],~S[0]);
and(f, F,S[2],~S[1],S[0]);
and(g, G,S[2],S[1],~S[0]);
and(h, H,S[2],S[1],S[0]);
or(Out, a,b,c,d,e,f,g,h);
endmodule
Hierarchical Combination of the Two
module shiftRegister_struct(
input clk,
input [2:0]S,
input [3:0]L,
output reg [3:0]V
);
wire a,b,c,d;
wire V_bar[3:0];
Mux8to1 stage3(S[2:0],V[3],V[0],V[2],1'b0,V[2],V[3],V[2],L[3],a);
Mux8to1 stage2(S[2:0],V[2],V[3],V[1],V[3],V[1],V[3],V[1],L[2],b);
Mux8to1 stage1(S[2:0],V[1],V[2],V[0],V[2],V[1],V[2],V[1],L[1],c);
Mux8to1 stage0(S[2:0],V[0],V[1],V[3],V[1],1'b0,V[1],1'b0,L[0],d);
D_Flip_Flop stage3b(a,clk,V[3],V_bar[3]);
D_Flip_Flop stage2b(b,clk,V[2],V_bar[2]);
D_Flip_Flop stage1b(c,clk,V[1],V_bar[1]);
D_Flip_Flop stage0b(d,clk,V[0],V_bar[0]);
end module
Any thoughts on what might be screwing up my output? The output is V[3:0].
I should also include my test bench code:
module Shift_Test_Bench;
// Inputs
reg [2:0] S;
reg [3:0] L;
reg clk;
integer i;
integer j;
// Outputs
wire [3:0] V;
// Instantiate the Unit Under Test (UUT)
shiftRegister_struct uut (
.clk(clk),
.S(S),
.L(L),
.V(V)
);
initial begin
// Initialize Inputs
S = 7;
L = 3;
clk = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i < 16; i = i+1)
begin
S = i;
for(j = 0; j < 2; j = j+1)
begin
clk = !clk;
#5;
end
end
end
endmodule
You have a wiring bug in your D_Flip_Flop module. When I simulated your testbench, I got compiler warnings:
Implicit wire 'f' does not have any driver, please make sure this is
intended.
Implicit wire 'e' does not have any driver, please make sure this is
intended.
Here are the lines:
nand(Q,d,f);
nand(Q_bar,b,e);
Your missing a reset condition, either synchronous or asynchronous. Your flops have an unknown value and never reach known state because the data input is dependent on the flop output. By adding a reset to can put the flops into a known state independent of its outputs (V/V_bar).
In this case adding a synchronous is be easier. Simply add some 2-to-1 muxes and a new reset pin.
Mux2to1 syncrst3(a_d,a,1'b0,reset);
// ...
D_Flip_Flop stage3b(a_d,clk,V[3],V_bar[3]);
// ...
I've been trying to build a module which returns the two's complement representation of the (3-bit) input (first bit being the sign). I think that the following code is correct conceptually, but I am probably missing something about it's structure: when I try to compile, I get the following errors:
(vlog-2110) Illegal reference to net "f_o".
(vlog-2110) Illegal reference to net "f_o".
(vlog-2110) Illegal reference to net "f_o".
Searching for that error showed it is usually seen when using a variable as input and output at the same time, but that's not my case. Could you point where the error is?
module ca2 (a_i,f_o);
input [2:0] a_i;
output [2:0] f_o;
always #(a_i[2:0] or f_o[2:0])
begin
if (a_i[2] == 1)
begin
f_o[2] = a_i[2];
f_o[1:0] = (~a_i[1:0] + 'b1);
end
else
begin
f_o = a_i;
end
end
endmodule
In Verilog, undeclared identifiers are considered implicit wire declarations in most circumstances. Since f_o has not been declared the compiler considers it a wire, not a variable. This causes the compiler to complain about all the assignments.
// What was typed
module ca2 (a_i,f_o);
input [2:0] a_i;
output [2:0] f_o;
// What the compiler implicitly declares
wire [2:0] a_i;
wire [2:0] f_o;
To fix it you can declare the variable or declare both the port and the variable.
module ca2 (a_i,f_o);
input [2:0] a_i;
output [2:0] f_o;
reg [2:0] f_o;
module ca2 (a_i,f_o);
input [2:0] a_i;
output reg [2:0] f_o;
f_o needs to be declared as a reg. output reg [2:0] f_o.
Also I am not sure what you are calculating, that is not a standard twos complement.
module ca2 (
input [2:0] a_i,
output [2:0] twos_comp,
output [2:0] also_twos_comp
);
assign twos_comp = ~a_i + 1'b1;
assign also_twos_comp = -a_i ;
endmodule
You may be dealing with an encoded input, but twos_complement is to negate the number I would expect the sign bit (MSB) to change. Although we refer to it as a sign bit it also contains information about the value and therefore can not just be stripped off and leave the number unchanged.
The first solution -> In sequential circuits, the output must be in the form of a reg.
and Next we need to know that in two's complement we start from bit zero to get to the end so the condition is incorrect.
If the zero bit is one, then the zero bit is unchanged and the rest of the bits change to not.
module ca2 (input [2:0] a_i,output reg [2:0] f_o);
always #(a_i[2:0] or f_o[2:0]) begin
if (a_i[0] == 1'b1) begin
f_o[0] = a_i[0];
f_o[2:1] = (~a_i[2:1]);
end
else
if(a_i[1]==1'b1) begin
f_o[1:0] = a_i[1:0];
f_o[2] = (~a_i[2]);
end
else
if(a_i[2] == 1'b1) begin
f_o = a_i ;
end
end
endmodule
The second solution -> In binary numbers, if we subtract the number from zero, we get two's complement .
module ca2 (input [2:0] a_i,output reg [2:0] f_o);
always #(a_i[2:0] or f_o[2:0]) begin
f_o = 3'b000 - a_i ;
end
endmodule
The third solution -> all bits change to not and Finally, they are added to the number one (3'b000 = 3'b0)
module ca2 (input [2:0] a_i,output reg [2:0] f_o);
reg [2:0] finish ;
always #(a_i[2:0] or f_o[2:0]) begin
finish = (~a_i);
f_o = finish + 3'b001 ;
end
endmodule