i wrote a truth table code in verilog and it show this error "varibale Y cannot be a net"
it is an equation to design a CMOS circuit it there any other way to declare the value of varibles instead of using the truth table? or is this method better if the error can be solved? this is the code down bellow
module pro1 ( A,B,C,D,E,Y);
output Y ;
input A,B,C,D,E ;
assign Y = ~(A&B^C&D^A&E&D^C&E&B);
always #(A or B or C or D or E)
begin
case ({A,B,C,D,E})
5'b00000:Y=0;
5'b00001:Y=0;
5'b00010:Y=0;
5'b00011:Y=0;
5'b00100:Y=0;
5'b00101:Y=0;
5'b00110:Y=1;
5'b00111:Y=1;
5'b01000:Y=0;
5'b01001:Y=0;
5'b01010:Y=0;
5'b01011:Y=0;
5'b01100:Y=0;
5'b01101:Y=1;
5'b01110:Y=1;
5'b01111:Y=1;
5'b10000:Y=1;
5'b10001:Y=0;
5'b10010:Y=0;
5'b10011:Y=1;
5'b10100:Y=0;
5'b10101:Y=0;
5'b10110:Y=1;
5'b10111:Y=1;
5'b11000:Y=1;
5'b11001:Y=1;
5'b11010:Y=1;
5'b11011:Y=1;
5'b11100:Y=1;
5'b11101:Y=1;
5'b11110:Y=1;
5'b11111:Y=1;
endcase
end
endmodule
Verilog only allows continuous assignments to wires na d procedural assignments to variables. For simple combinational logic, the two following descriptions are identical in functionality.
module pro1 ( input wire A,B,C,D,E,
output wire Y);
assign Y = ~(A&B^C&D^A&E&D^C&E&B);
endmodule
module pro1 ( input wire A,B,C,D,E,
output reg Y);
always #(*)
Y = ~(A&B^C&D^A&E&D^C&E&B);
endmodule
See https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/
Related
i am learning verilog and i am doing practice questions on https://hdlbits.01xz.net/wiki.
one of the questions is:
so my answer was:
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire and_ab;
wire and_cd;
wire or_out;
and(and_ab,a,b);
and(and_cd, c, d);
or(or_out, and_ab, and_cd);
assign out= or_out;
not(out_n,or_out);
endmodule
which is correct without any doubt, but their answer is:
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1, w2; // Declare two wires (named w1 and w2)
assign w1 = a&b; // First AND gate
assign w2 = c&d; // Second AND gate
assign out = w1|w2; // OR gate: Feeds both 'out' and the NOT gate
assign out_n = ~out; // NOT gate
endmodule
my question is how can it be possible they use 'output' wire as an 'input' to an assign in the same module? its not reg to hold it value, not that i know if you can do it with reg as an 'output' type.
Verilog and SV allow the reading of outputs from within a module.
It is different than VHDL which does not allow the same.
(Verilog) The following is a 32-bit Arithmetic Logic Unit (ALU) [see slides]. It has two 2-1 and one 3-1 MUX, a 32-bit Adder, a 32-bit subtractor, and a 16-bit multiplier. The function table shows different functions this ALU performs for different values of F (a 3-bit control signal). Notice the interconnect among different modules inside the ALU.
Please describe this ALU using Verilog. Your implementation should start with the smaller blocks showing in the ALU, and then using those smaller blocks to build the whole ALU. In other words, your implementation should promote reusability of smaller modules (i.e., modular). Optimize your implementation if possible.
function table in the image
module adding(r,a,b);
input[31:0] a;
input[31:0] b;
output[31:0] r;
assign r=a+b;
endmodule
module ALU(F,A,B,R);
input[2:0] F;
input[31:0] A;
input[31:0] B;
output[31:0] R;
reg R;
always #(F)
begin
if ( F == 3'b000 ) adding ad(R,A,B);
else if ( F == 3'b001 ) R = A+1;
else if ( F == 3'b010 ) R = A-B;
else if ( F == 3'b011 ) R = A-1;
else if ( F == 3'b10x ) R = A*B;
end
endmodule
this what I did so far but I got errors!! I will continue with the other statement as I know how to make the first small module
Notice some basic verilog syntax issues.
bit width mismatch in declaration of R.
sensitivity list not complete for the always block.
module instantiation is not allowed under a structural if.
I don't know if the undefined branches for F is intended, it is leading to behavior perhaps your don't want.
Since you are mainly working on module partition, it's related to the point 3. You will need to instantiate the basic (reusable) modules separately, and then select the outputs via F.
wire [31:0] adder_b;
wire [31:0] adder_result;
assign adder_b = F[0] ? 32'h1 : B; // select input outside 'adding'
adding ad (adder_result, A, ader_b);
always#(*)begin
if(F2:1] == 2'b00) R = adder_result;
...
end
There are many ways to write simple code in verilog.it depends on requirement some time here I presented different ways to write this code.
first by assign keyword and the second by case statements.
assign result = (opcode==3'b000) ? A+B :
((opcode==3'b001)? A+1 :
((opcode==3'b010)? A-B :
((opcode==3'b011)? A-1 : A*B)));
always #(*) begin
casex(opcode)
3'b000: result=A+B;
3'b001: result=A+1;
3'b010: result=A-B;
3'b011: result=A-1;
3'b1xx: result=A*B;
endcase
end
I am trying to wire a Verilog Structural description of an Edge-triggered T flip-flop with an synchronous reset (R). Here is the circuit for this element:
Now assume that I have already written the behavioral description for each block in this schematic , so here is my structural description for this circuit by instantiation of each of this blocks in the circuit:
module edge_trig_flipflop_structure (
input x,y,clk,
output q,
wire a,b,c,d
);
inv u1(c,q);
mux_2x1 u2 (q,c,x,a);
inv u3(d,y);
and_2_1 u4(b,a,d);
d_flipflop u5(b,clk,q);
endmodule
Is this a good efficient code for this circuit? In other words, do I really need the two extra wires used for the inverters which are the wires c and d Or, is there another efficient way to write this code?
Edit : Here is the code for each component to know the order of ports in the declaration of each component
module mux_2x1 (
input a,
input b,
input sel,
output reg c
);
always # (*) begin
case ( sel)
1'b0: c=a;
1'b1: c=b;
default : $dispaly ("error");
endcase
end
endmodule
module d_flipflop ( input d,clk , output reg q);
always # (posedge clk ) begin
q=d;
end
endmodule
module inv(output reg b, input a);
always # (a) begin
b=~a;
end
endmodule
module and_2_1 ( output reg c,input a,b);
always #(a or b) begin
if (a==1'b1 & b==1'b1)
c= 1'b1;
else
c=1'b0;
end
endmodule
By default, Verilog does not require you to declare all signals. If signals appear in port connections, they will implicitly be 1-bit wire types.
However, it is good practice to declare all signals explicitly with wire, as you have done.
You could also change the default behavior and require explicitly declared signals using this compiler directive:
`default_nettype none
Since you are also concerned about connections, it is a good practice to make connections by name instead of connections by position. It is more verbose, but it will help avoid simple connection errors. For example:
inv u1 (.b(c), .a(q));
I got compile errors on your module header. You probably meant to code it this way:
module edge_trig_flipflop_structure (
input x,y,clk,
output q
);
wire a,b,c,d;
I'd like to make a simple module in verilog
The scheme is this.
If(en)
A=B;
else
B=A;
I want to implement to verilog without clock.
Could it be possible to implement the above logic?
update
I want to sum of 2 inout ports.
But I'm not sure how. Would you let me know how can I make sum of 2 inout ports?
Module test1(
en,
A,
B,
C
);
input en;
inout [1:0] A;
inout [1:0] B;
output [3:0] C;
...
What can I do ?
...
endmodule
If(en)
A=B;
else
B=A;
You can't sum the two inout ports A and B. en determines the direction.
Consider this code:
assign A = (en) ? B : 1'bz;
assign B = (~en) ? A : 1'bz;
When en is low, B will be your output and A will be your input.
When en is high, A will be your output and B will be your input.
Your output C will be undefined when you assign the sum of A and B since either of the input is 1'bz.
assign C = A + B; // will cause undefined behavior
How do I convert a tristate bus to 2-state logic for synthesis?
I've made a little test
module test1( inout tristate, output flattened);
assign flattened = tristate ? 1 : 0;
endmodule
module test2( inout tristate, output reg flattened);
always #(tristate) begin
case(tristate)
0: flattened = 0;
default: flattened = 1;
endcase
end
endmodule
`timescale 1ns / 1ps
module test_tb;
reg tristateEnable;
reg tristateValue;
wire tristate = tristateEnable ? tristateValue : 1'bz;
wire flattened1, flattened2;
test1 uut1(tristate, flattened1);
test2 uut2(tristate, flattened2);
initial begin
tristateValue = 1'b0;
tristateEnable = 1;
#10 tristateValue = 1'b1;
#10 tristateEnable = 1'b0;
end
endmodule
Simulating it I got that module test1 sets flattened to X and module test2 sets it to 1, the latter is what I wanted, but I haven't synthesized it yet. Is there a better / standard way of doing this?
You've asked two questions: (1) what is the difference between the conditional operator and the case statement, and (2) how to handle tri-state values.
On the language question:
In short, Verilog has a 4-state data type, and the operators handle the 4 states differently.
The case statement does a "4-state test", otherwise known as "case equality". The case expression (tristate in your example) is compared against 0, 1, x, and z. When it is z, the default branch is taken, so flattened is 1, as you found.
The conditional ('ternary') operator also does a 4-state test, and finds tristate as z. It doesn't know what to do now, so it combines the two values you supplied (0 and 1) into a resulting x, which is what you see. Basically, it's trying to be smart. See table 5-21 in the 2005 LRM.
Note that the if statement does not do a 4-state test.
Tristates: you're confused because your control signal (tristate) goes to z; it's the data signal (flattened) that should go to z.
You don't 'flatten' tristates for synthesis; you normally model a pull-up or pull-down. This will be specific to your technology, but you may just need to instantiate a pullup or pulldown component. Your synthesiser may or may not do this automatically for you if you have code like
assign sig_o = (ena == 1'b1)? sig_i : 1'bz;
You need to read your synthesiser docs to be sure. Note that you should only ever use a conditional operator like this if ena is guaranteed to be 2-state (0/1).