Makefile pattern rule not working properly - linux

Long story short, it seems like pattern rules are not behaving correctly.
Assume you have simple Makefile like this,
%.o:
gcc $< -o $#
echo from %.o
and if you type make asd, which clearly doesn't match %.o pattern, it will actually match asd.o and performe recipe for it.
[user]$ make asd
gcc -o asd.o
gcc: fatal error: no input files
compilation terminated.
make: *** [Makefile:2: asd.o] Error 1
So you get this output.
But even stranger thing is that if you explicitly disable the builtin rules by --no-builtin-rules flag, it won't match.
[user]$ make --no-builtin-rules asd
make: *** No rule to make target 'asd'. Stop.
I have no idea why enabling or disabling builtin rule should do anything about pattern matching, so does anyone have idea why this is happening?
P.S. I'm using GNU Make 4.3 in Arch Linux (don't know kernel version).

which clearly doesn't match %.o pattern
You've specified that to create asd.o you have no dependencies so it will try to create it from your recipe directly.
If you have dependencies, like "to create asd.o there must be an asd.c file", then specify that by adding a dependency:
%.o: %.c
gcc $< -c -o $#
#echo from $#
Note: I added -c to make it into a plain object file, not an executable.
If you now do make --no-builtin-rules asd.o and if you don't have asd.c, it will print:
$ make --no-builtin-rules asd.o
make: *** No rule to make target 'asd.o'. Stop.
If you on the other hand do have asd.c, it'll use your recipe to create asd.o:
$ make --no-builtin-rules asd.o
gcc asd.c -o asd.o
from asd.o
You may want to add a rule for creating an actual executable too - and if you don't want the built-in rules, you can create an empty target for .SUFFIXES:
.SUFFIXES:
%: %.o
gcc -o $# $<
echo from $#
%.o: %.c
gcc $< -c -o $#
#echo from $#
Now, it'll first create asd.o and then link that into asd if you do make asd:
$ make asd
gcc asd.c -c -o asd.o
from asd.o
gcc -o asd asd.o
echo from asd
from asd
rm asd.o

Related

Compiling with SDCC fails with -Wall option

I'm compiling a 8051 project with SDCC but has a problem with Makefile, the following sources:
TARGET = test
CC = sdcc
CFLAGS = -Wall -I.
RM = rm -rf
SRCS = $(wildcard *.c)
RELS = $(patsubst %.c,%.rel,$(SRCS))
$(TARGET).bin: $(TARGET).hex
objcopy -I ihex -O binary $< $#
$(TARGET).hex: $(TARGET).ihx
packihx $< > $#
$(TARGET).ihx: $(RELS)
#echo Linking ...
$(CC) $(CFLAGS) $< -o $#
#echo Build finish!
%.rel: %.c
#echo Compiling ...
$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
#echo Removing ...
$(RM) *.rel *.ihx *.lk *.lst *.map *.mem *.rst *.sym *.asm $(TARGET)
#echo Removed!
When I run make it has errors:
minh#PCDESIGN:~/workspaces/programMSC51/test$ make
Compiling ...
sdcc -Wall -I. -c main.c -o main.rel
sdas Assembler V02.00 + NoICE + SDCC mods (Intel 8051)
Copyright (C) 2012 Alan R. Baldwin
This program comes with ABSOLUTELY NO WARRANTY.
Usage: [-Options] file
Usage: [-Options] outfile file1 [file2 file3 ...]
-d Decimal listing
-q Octal listing
-x Hex listing (default)
-g Undefined symbols made global
-a All user symbols made global
-b Display .define substitutions in listing
-bb and display without .define substitutions
-c Disable instruction cycle count in listing
-j Enable NoICE Debug Symbols
-y Enable SDCC Debug Symbols
-l Create list file/outfile[.lst]
-o Create object file/outfile[.rel]
-s Create symbol file/outfile[.sym]
-p Disable automatic listing pagination
-u Disable .list/.nlist processing
-w Wide listing format for symbol table
-z Disable case sensitivity for symbols
-f Flag relocatable references by ` in listing file
-ff Flag relocatable references by mode in listing file
-I Add the named directory to the include file
search path. This option may be used more than once.
Directories are searched in the order given.
removing
make: *** [Makefile:22: main.rel] Error 1
How can I fix this?
Unlike other compilers, SDCC does not have a -Wall option. You should remove it from CFLAGS = -Wall -I. in the Makefile.
It also does not have a replacement. There are options --less-pedantic and -Werror, which gives you fewer warnings, or treats warnings as errors, respectively, but there is no option for creating more warnings.
The manual mentions --more-pedantic, but
Actually this is not a SDCC compiler option but if you want more warnings you can use a separate tool dedicated to syntax checking [...]
See SDCC Compiler User Guide (version 4.1.12), section 3.3.4.

specifying the filename in a makefile

I'm new to this and trying to create a makefile where I could, for example, run:
make -f mymakefile testfile
and the makefile would find testfile.java (which exists in the directory I'm running from), compile it, and run the code.
Instead, I must be confused with how automatic variables work and after working all afternoon I still get the error:
make: Nothing to be done for `testfile'.
Any help would be appreciated and my code is below:
JC=javac
JVM=java
JFLAGS= -g
RM = rm -f
CFLAGS =
CXX = gcc
NAME = *
.SUFFIXES: .java .class
all: run
NAME:
$(CXX) $(CFLAGS) -o $^ $#
echo $(NAME)
$(NAME).class: $(NAME)
$(JC) $(JFLAGS) $(NAME).java
run: $(NAME).class
$(JVM) $(NAME)
.PHONY: clean
clean:
$(RM) $(NAME).class
I've tried just having it echo 'testfile' to better understand how automatic variables work, but I couldn't get that to work correctly either.
The arguments on the make command line select the targets to build. You can't pass values to variables in the same way you would with a shell script (like you're trying to do with "NAME".)
If you really want to pass a value for a variable, the command would be:
NAME=testfile make -f mymakefile
You can use pattern rules to create rules from arbitrary names. For example:
%.bin : %.cpp
$(CXX) $(CXXFLAGS) -o $# $<
When you call make test.bin, this matches pattern rule %.bin, where % matches test. Then automatic variables $< substitutes the source file and $# substitutes the target file. What actually runs is something like g++ -O3 -o test.bin test.cpp.

Makefile error in C linux

I have an error while making my makefile in linux. Here's my code:
CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
SHELL_SOURCES = Shell.c
SHELL = Shell
.PHONY: all target1 clean
all: target1
target1: $(SHELL)
$(SHELL): $(SHELL_SOURCES)
$(CC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(SHELL)
The error I get is:
gcc -Wall -m32 -g -fno-stack-protector -z execstack -O0 Shell.c -o Shell
make: Shell: Command not found
Makefile:16: recipe for target 'Shell' failed
make: *** [Shell] Error 127
You can't use SHELL as a variable in a Makefile, it is used to know what shell (/bin/sh, /bin/bash, etc) will be used in your Makefile.
CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
EXE_SOURCES = Shell.c
EXE = Shell
.PHONY: all target1 clean
all: target1
target1: $(EXE)
$(EXE): $(EXE_SOURCES)
$(CC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(EXE)
Take more time to read documentation of GNU make
You should remove spaces around variable assignments, e.g. code
CC= gcc
Beware that tab characters are significant in Makefile-s (in rules, for their action lines). Use some editor aware of that (e.g. emacs has a mode for Makefile). See also this example (but the rule action should really start with a tab character). Notably, you need a tab just before the $(CC) $(CFLAGS) $^ -o $# and another one before rm.
Consider also using remake -x to debug your Makefile, or at least make --trace
But the main bug was indeed, as answered by Cpatricio, to use the SHELL variable. Be careful when using variables or names already known to make. Actually, I have the habit of prefixing my make variable names with a common prefix, so you could have defined your variables like JOJOIGA_SOURCES=$(wildcard *.c), JOJOIGA_SHELL=Shell etc....

Compiling C++ and C files in one makefile

I have a makefile that looks like this:
CS := a.c b.c
CPPS := foo.cpp bar.cpp
SOURCES := $(CS) $(CPPS)
OBJS := $(CS:%.c=$(OBJSDIR)/%.o) $(CPPS:%.cpp=$(OBJSDIR)/%.o)
I want to create a single rule to compile them all. But the only option I can think of is this:
$(OBJSDIR)/%.o: %.cpp
$(GXX) $(GXXFLAGS) -c $< -o $#
But of course it doesn't work because some of the object files don't have a matching C++ source file.
Any idea?
suppose you have a.cc, b.cc and c.cc, and on the other side, d.c, e.c and f.c
program_objs = a.o b.o c.o d.o e.o f.o
program: $(program_objs)
$(CC) $(LDFLAGS) -o $# $(program_objs)
You don't need anything more, as make will automatically detect which files are c++ and which ones are plain c and will select the proper compiler.
in case you want something special, not included in makefile, you can add some suffixes (file types) with the rule:
.SUFFIXES: .a .b .o
and then use the following rules to compile them to .o
.a.o:
$(COMPILER_A) $(COMPILER_A_FLAGS) -c $# -o $<
.b.o:
$(COMPILER_B) $(COMPILER_B_FLAGS) -c $# -o $<
and let makefile select the proper compiler (the one stored in variables COMPILER_A or COMPILER_B) to do the work.
Of course, you can compile something to a .o file with an explicit rule, as in:
a.o: a.cc
g++ -o a.o -c a.cc
b.o: b.cc
g++ -o b.o -c b.cc
c.o: c.cc
g++ -o c.o -c c.cc
d.o: d.c
gcc -o d.o -c d.c
e.o: e.c
gcc -o e.o -c e.c
f.o: f.c
gcc -o f.o -c f.c
Note #1:
Some sugestions have been made on GNU make % pattern to construct implicit rules for targets. Below is a rewritting of the implicit rules above to do the same thing:
%.o: %.a
$(COMPILER_A) $(COMPILER_A_FLAGS) -c $# -o $<
%.o: %.b
$(COMPILER_B) $(COMPILER_B_FLAGS) -c $# -o $<
As always, $# means the target of the rule and $< (you can use also $* for the file name without any matching suffixes) the left needed file. For a complete list of automatic variables that can be used, I suggest you to read your make manual. Take into account that the old suffix syntax is reversed from the new one (the target suffix appears last in the old syntax, the new syntax being more similar to a normal makefile rule with the target on the left side of the colon)
I want to create a single rule to compile them all.
As Etan Reisner said in the comment section, make already has implicit rules to compile .c and .cpp file, so the real answer to your question is:
Do not write anything to compile your object files.
That said, you should now remove those two variables: $(GXX) and $(GXXFLAGS).
To provide flags to cc or gcc one should use the CFLAGS built-in variable.
To provide flags to g++ one should use the CXXFLAGS built-in variable.
To provide flags to the preprocessor (cpp) one should use the CPPFLAGS variable.
Since you're mixing C and C++ source files, you should use the CXX variable as the linker command.

makefile not generating executeble files

I am fairly new at makefile. I am trying to create a makefile that compiles yu.c and link yu.c to get a executable file called yu.
Below is the code i have. I am using make -f mymakefile to run the file and each time i run it, only gcc -c yuFile.c is done.
Where am I wrong?
CC=gcc
yu.o: yuFile.c
${CC} -c yuFile.c
yu: yuFile.o
${CC} yu -o yuFile.o
run-c: yu
./yu
clean:
rm -f "*.o" core
make with no target specified makes the first target in the file, so in your case it is equivalent to make yu.o.
Typically, you make the first target all so that everything is built:
all: yu
.PHONY: all
(Note that the .PHONY prevents make from doing nothing if there's a file named all already).
Worth pointing out: you've got your arguments reversed in the yu target. It should be
yu: yuFile.o
${CC} yuFile.o -o yu
or more generically
yu: yuFile.o
${CC} $^ -o $#
($^ means all prereqs, and $# means the target, as documented in Automatic Variables).
The first target is the one picked when no argument is specified.
The standard is to have an 'all' target first:
all: yu
Also, your 'yu' target is incorrect.
yo: yufile.o
$(CC) -o $# $^
should work

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