Adding an MMIO peripheral to Rocket-chip as a submodule - riscv

Question

I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower pace on the pages of the Chisel Learning Journey <== adding that only if the person answering question may want to take a look and see that I've got everything working correctly. In other words, I added the MMIO with in the example package of Chipyard and it compiles, generates simulator, responds properly to toy benchmark I devised, I even see the corresponding waveforms in gtkwave.
Now, the next step I would like to take is to separate this dummy design (it literally just reads from a memory mapped register that holds a hardcoded value) from the chipyard/rocket-chip infrastructure in the sense that it is housed in a separate repo, that will become a submodule of my chipyard. So, to do that, I've started from this page and took all the steps as given there:
a new repo was created, called it my-chip
into the my-chip I added build.sbt of the following content:
organization := "My Chip"
version := "1.0"
name := "my-chip"
scalaVersion := "2.12.10"
into the my-chip I added src/main/scala/JustRead.scala the one built through the mentioned pages of the Learning Journey
within the JustRead.scala I only replaced the package line so that now it is:
package my-chip
then, I added the my-chip repo as a submodule to path: chipyard/generators/my-chip
finally I added appropriate lines to chipyard/generators/chipyard/src/main/scala/DigitalTop.scala as follows:
package chipyard
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends System
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with my-chip.CanHavePeripheryJustRead // <=== ADDED THIS LINE
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with icenet.CanHavePeripheryIceNICModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with my-chip.CanHavePeripheryJustReadTopModuleImp // <=== AND THIS LINE
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop
Then, I created a config in chipyard/generators/chipyard/src/main/scala/configs/RocketConfig.scala as follows:
class JustReadTLRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithUART ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new my-chip.WithJustRead ++ // <=== THIS LINE ADDED
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
Finally, I changed the main build.sbt the one in chipyard root to hold these lines additionally:
lazy val my-chip = (project in file("generators/my-chip"))
.dependsOn(rocketchip, chisel_testers, midasTargetUtils)
.settings(commonSettings)
and
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
my-chip, // <=== ADDED THIS
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla)
.settings(commonSettings)
Now, when running make CONFIG=JustReadTLRocketConfig, I get the following error:
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
Picked up _JAVA_OPTIONS: -Xmx2048m
[info] Loading settings for project chipyard-build from plugins.sbt ...
[info] Loading project definition from /home/apaj/chipyard/project
[error] [/home/apaj/chipyard/build.sbt]:166: Pattern matching in val statements is not supported
Looking around didn't really help as I am lacking any scala/software building skills, so couldn't make much of this, for example...
My spider sense tells me I messed up something in the paths within internal organization of the chipyard, so... please, some help from an experienced user would be much appreciated. Thanks.
EDIT: typos and adding point 8.

Answer 1

The error comes from the - in lazy val my-chip and package my-chip. If you want to use a - in a scala name you can wrap the name in backticks, like `my-chip`.