Verilog test bench for 4-bit adder with Carry Lookahead [duplicate] - verilog

Question

This question already has answers here:
Can anyone help me to create a Verilog testbench?
(2 answers)
Closed 1 year ago.
I'm still honestly a bit unfamiliar with Verilog especially with test benches, considering I've only created a childishly simple project once. I'm not sure how to make a test bench for a Verilog file I've made and so I can't test if it works. Here's my code:
`timescale 1ns/1ps
module adder_4bit_cla(sum, Cout, A, B, S);
input [3:0] A, B;
input S;
output [3:0] sum;
output Cout;
wire P0, G0, P1, G1, P3, G3;
wire C4, C3, C2, C1;
assign
P0 = A[0] ^ B[0],
P1 = A[1] ^ B[1],
P2 = A[2] ^ B[2],
P3 = A[3] ^ B[3];
assign
G0 = A[0] & B[0],
G1 = A[1] & B[1],
G2 = A[2] & B[2],
G3 = A[3] & B[3];
assign
C1 = G0 | (P0 & S),
C2 = G1 | (P1 & G0) | (P1 & P0 & S),
C3 = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & S),
C4 = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & S);
assign
sum[0] = P0 ^ S,
sum[1] = P1 ^ C1,
sum[2] = P2 ^ C2,
sum[3] = P3 ^ C3;
assign Cout = C4;
endmodule
Honestly, what I really need to do is a 4-bit adder-subtractor using carry lookahead, but I have no idea how to implement a carry lookahead to begin with so here I am. If anyone could help me that would be really great :<
Edit: I have calmed down and I can finally pinpoint the exact problem: the values of A and B for the test bench. While I could brute force it, how can I make use of loops to increment A and B so that it would be like this:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
While also updating M?

Answer 1

Use the following to improve your testbench.
`timescale 1ns / 1ps
module adder_4bit_cla_tb();
// inputs - keep them having reg as the data type
reg [3:0] A, B;
reg S;
// outputs - keep them having wire as the data type
wire [3:0] sum;
wire Cout;
adder_4bit_cla adder_4bit_cla_inst
(
.sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
);
initial begin
A = 4'd1; B = 4'd2; S = 1'd1;
#10 A = 4'd2; B = 4'd5; S = 1'd0;
#10 A = 4'd5; B = 4'd6; S = 1'd0;
#50 $stop;
end
endmodule
Waveform results
Inputs can be fed using for loops as follows.
`timescale 1ns / 1ps
module adder_4bit_cla_tb();
// inputs - keep them having reg as the data type
reg [3:0] A, B;
reg S;
// outputs - keep them having wire as the data type
wire [3:0] sum;
wire Cout;
reg [3:0] i;
adder_4bit_cla adder_4bit_cla_inst
(
.sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
);
initial begin
for(i = 4'd0; i < 4'd15; i = i + 4'd1) begin
A = i; B = i; S = 1'b0;
#10;
end
#200 $stop;
end
endmodule
Waveform Results