I am implementing SR latch without clock signal using Verilog. I am trying with the code given below, but I am getting the value of Qb as X. Please help me.
// design.v file
module sr_latch(q,qb,s,r);// module declaration
input s,r;
output q,qb;
assign qb=~q;
nand (q,s,qb);
nand (qb,r,q);
endmodule
// testbench.v file
module stimulus;
reg set,reset;
wire Q,Qb;
sr_latch mylatch(Q,Qb,set,rest);
initial
begin
$dumpfile("dump.vcd");
$dumpvars;
$monitor($time,"set=%b,reset=%b,Q=%b,Qb=%b\n",set,reset,Q,Qb);
set=0; reset=0;
#5 set=0; reset=1;
#5 set=1; reset=0;
#5 set=1; reset=1;
end
endmodule
Result:
0set=0,reset=0,Q=1,Qb=x
5set=0,reset=1,Q=1,Qb=x
10set=1,reset=0,Q=x,Qb=x
15set=1,reset=1,Q=x,Qb=x
There are 2 errors in your code.
In your design file, you have 2 drivers for the qb signal, but you should only have 1. You should delete the following line:
assign qb=~q;
You have a typo in the testbench; I got a compile warning about this in one of the simulators on edaplayground. You misspelled reset as rest. Change:
sr_latch mylatch(Q,Qb,set,rest);
to:
sr_latch mylatch(Q,Qb,set,reset);
Result:
0set=0,reset=0,Q=1,Qb=1
5set=0,reset=1,Q=1,Qb=0
10set=1,reset=0,Q=0,Qb=1
15set=1,reset=1,Q=0,Qb=1
Related
While implementing the Verilog code you are seeing below, I have encountered an error message as follows:
** Error: (vish-4014) No objects found matching 'a'.
# Error in macro ./sim.do line 4
# (vish-4014) No objects found matching 'a'.
# while executing
# "add wave a"
Can you tell how to fix the problem or where I do wrong?
The code is intended to do a multiply and accumulate task implemented on Model-sim SE-64 10.6d
//mac implemetation
module mac(
output reg[15:0] out,
input[7:0] ina,inb,
input clk,sclrn
);
endmodule
//mac testbench
`timescale 1ns /1ns
module mac_tb();
//togle clock
reg clk;
initial begin
clk = 0;
forever #80 clk = ~clk;
end
reg sclrn;
initial begin
sclrn =0;
#350 sclrn=1;
end
reg[7:0] a,b;
wire[15:0] dout;
mac DOT(.ina(a),.inb(b),.clk(clk),.sclrn(sclrn),.out(dout));
endmodule
the sim.do file for simulation
vlib work
vlog mac.v mac_tb.v
vsim work.mac_tb
add wave a
add wave b
add wave dout
add wave clk
add wave sclrn
run 1000
Look in the ModelSim User manual for "Preserving Object Visibility" and add the switch it recommends.
I am quite new to verilog and active-hdl. I have got a problem and I would appreciate it if someone could advise me on this.
I can't see the waveforms of second layer modules on waveform viewer. More precisely, the signals in submodules show either Z or X.
Please note that I have enabled read/write access through tools/preferences/simulation/ access design object.
For example I am generating a clk in tb module and connect it to clk_mod, trying to see the clk in clk_mod, however for clk it shows only "Z" and for "i" only "X".
`timescale 1ns/100ps
module tb;
reg clk;
clk_mod dut(.clk(clk));
initial
begin
clk = 0;
forever
#5 clk = ~clk;
end
endmodule
module clk_mod (input clk);
reg i;
always #(posedge clk)
begin
i=10;
end
endmodule
I think that your tb is lacking exit from simulation. you should add the following statement to the tb module (as a separate statement):
initial #20 $finish;
This would finish simulation at step 20 and should create waveforms for you, if you use right tools.
Also, you declared i as a single-bit reg, so, you cannot fit '10' in to it. So, your waveform should show toggling clock and a single transaction of 'i' from 'x' to '0'.
I guess you should have declared 'i' as this:
reg [3:0] i;
I have been designing a basic full adder with two half adder modules and trying to test it with a testbench. There are no compile errors, but at the output (Waveform), I get Z and X for Sum and Carry. I am stuck and not sure what next to look at to correct this error.
Any advice in what next steps (or some pointers) to be checked in order to rectify this would be helpful.
Here is the Verilog code for the Full Adder:
module half_adder(x,y,S,C);
input x,y;
output S,C;
xor G1(S,x,y);
and G2(C,x,y);
endmodule
module full_adder(x,y,z,S,C);
input x,y,z;
output S,C;
wire S1,C1,C2;
half_adder HA1(S1,C1,x,y);
half_adder HA2(S,C2,S1,z);
or G3(C,C1,C2);
endmodule
Testbench for the above:
module tb_fulladder;
wire S,C;
reg x,y,z;
full_adder DUT(x,y,z,S,C);
initial
begin
x=1'b0;y=1'b0;z=1'b0;
#50
x=1'b0;y=1'b0;z=1'b1;
#50
x=1'b0;y=1'b1;z=1'b0;
#50
x=1'b0;y=1'b1;z=1'b1;
#50
x=1'b1;y=1'b0;z=1'b0;
#50
x=1'b1;y=1'b0;z=1'b1;
#50
x=1'b1;y=1'b1;z=1'b0;
#50
x=1'b1;y=1'b1;z=1'b1;
end
initial
#500
$finish;
endmodule
Here is the waveform:
You made a mistake in your connections to half_adder. You need to change the order of the port signals. Change:
half_adder HA1(S1,C1,x,y);
half_adder HA2(S,C2,S1,z);
to:
half_adder HA1 (x,y,S1,C1);
half_adder HA2 (S1,z,S,C2);
I discovered this by looking at the waveforms for the internal full and half adder signals.
This is why it is better to use connection-by-name instead of connection-by-position. For example, use:
half_adder HA1 (.x(x), .y(y), .S(S1), .C(C1));
Using this syntax, the port order does not matter. Refer to the free IEEE Std 1800-2012, 23.3.2 Module instantiation syntax.
I can't put my finger on why is it not working. I ran a simulation on edaplayground, and I get an "x" in the output every time the select changes to 0. I properly get "1" when sel is "1" though.
The code:
module mux8_2(input [3:0]a,[3:0]b,sel,output [3:0]out);
assign out=(sel)?a:b;
endmodule
and the testbench:
module mux8_2_tb;
reg [3:0]A;
reg [3:0]B;
reg SEL;
wire [3:0]OUT;
mux8_2 UUT(A,B,SEL,OUT);
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
A=4'b1; B=4'b0; SEL=1'b1;
#1 SEL=1'b0;
#1 SEL=1'b1;
#1 SEL=1'b0;
#1 SEL=1'b1;
#1 SEL=1'b0;
#1 SEL=1'b1;
#1;
end
endmodule
I can't reproduce your results; the OUT signal is always known for me.
But, I do get a compile warning:
The following 1-bit expression is connected to 4-bit port "sel" of module
"mux8_2", instance "UUT"
This can be fixed:
module mux8_2(input [3:0]a,[3:0]b, input sel,output [3:0]out);
In your code sel inherited the width from the previous signal ([3:0]b). Your code is equivalent to:
module mux8_2(input [3:0]a,[3:0]b,[3:0]sel,output [3:0]out);
Adding another input keyword before sel forces it to use the default width of 1 bit.
I'm having problems on how to create a test module for the following Verilog code:
module Multiplier_4bit(output [8:0] y, input [3:0] i1, input [3:0] i2);
assign y=i1*i2;
endmodule
I thought of the following test module:
module M4_Tester
reg [3:0] i1;
reg [3:0] i2;
wire [9:0] y;
initial begin
i1=5;
i2=3;
$finish();
Multiplier_4bit device1(
.out(y),
.in0(i1),
.in1(i2)
);
endmodule
Please correct me if I'm wrong and sorry for bad english, as I am not a native speaker.
Thanks in advance.
You cannot instantiate a module inside of a begin block (put the multiplier somewhere outside of your initial begin block.
You have no corresponding end which closes the initial begin block.
Your simulation will terminate instantly because there is no delay between setting the values and the $finish. Put some nominal time delay before the simulation finishes with #10 $finish().
Next time please clarify your question before asking, and post the actual error messages you are receiving.