I am quite new to verilog and active-hdl. I have got a problem and I would appreciate it if someone could advise me on this.
I can't see the waveforms of second layer modules on waveform viewer. More precisely, the signals in submodules show either Z or X.
Please note that I have enabled read/write access through tools/preferences/simulation/ access design object.
For example I am generating a clk in tb module and connect it to clk_mod, trying to see the clk in clk_mod, however for clk it shows only "Z" and for "i" only "X".
`timescale 1ns/100ps
module tb;
reg clk;
clk_mod dut(.clk(clk));
initial
begin
clk = 0;
forever
#5 clk = ~clk;
end
endmodule
module clk_mod (input clk);
reg i;
always #(posedge clk)
begin
i=10;
end
endmodule
I think that your tb is lacking exit from simulation. you should add the following statement to the tb module (as a separate statement):
initial #20 $finish;
This would finish simulation at step 20 and should create waveforms for you, if you use right tools.
Also, you declared i as a single-bit reg, so, you cannot fit '10' in to it. So, your waveform should show toggling clock and a single transaction of 'i' from 'x' to '0'.
I guess you should have declared 'i' as this:
reg [3:0] i;
Related
It is a simple asynchronous 2 bit counter, two JK flipflops are being used.
Here is my TwoBitCounter.v script.
`timescale 1ns / 1ps
module TwoBitCounter(
input wire clk,
output wire q0,
output wire q1
);
JK jk1(1, 1, clk, q0);
JK jk2(1, 1, q0, q1);
endmodule
module JK(
input wire J,
input wire K,
input wire clk,
output reg out
);
always #(posedge clk) begin
if(J==0&&K==0)
begin end
else if(J==0&&K==1) begin
out <= 1'b0;
end else if(J==1&&K==0) begin
out <= 1'b1;
end else if(J==1&&K==1) begin
out <= ~out;
end
end
endmodule
and this is my simulation code :
`timescale 1ns / 1ps
module TwoBitCounter_sim();
reg clk;
wire q0;
wire q1;
TwoBitCounter twoBitCounter(.clk(clk), .q0(q0));
initial clk = 1'b0;
always clk = #100 ~clk;
initial begin
#1000;
$finish;
end
endmodule
I have checked that JK module works properly alone. I tried disabling one JK flip flop to see if it has no errors while implemented in TwoBitCounter module, and it also did not work. Although I have checked several times to see if the algorithm itself is wrong, but got no clue what the fundamental problem is.
In your code there is only one J/K combination which you use: 1/1. In this state you just invert the out (out <= ~out). However you had never initialized it. Your out initially has x value. Inversion of x is also x. So, it never changes.
You need to figure out a way to initialize the flops either by manipulating J/K values or by other means.
As an example, adding initial out = 0; in the JK module will change the picture, but it will not play well with synthesis. So, you need to figure out your own way.
I was trying to teach myself verilog programming from "The Verilog HDL" book by Thomas Moorby. In one of the exercises, they asked to generate a clock using structural verilog only (except for the $monitor part of course).
I tried the following:
module clock();
wor clk;
assign clk=0;
initial begin
$monitor($time,,"clk=%b", clk);
#100 $finish;
end
assign #5 clk = ~clk;
endmodule
Problem is, it works in iVerilog 0.9.7, but for version 10.0 and above, it does not work.. I simply get undefined value for clk!
Does not seem like a bug in iVerilog, otherwise it would probably have been fixed in one of the 10.x releases. Is there any other way to get this working? Also, what is wrong with the current code (if any) ?
this is a messy code you have. usually clock generation done with regs as one of the following
reg clk;
initial begin
clk = 0;
forever
#5 clk = ~clk;
end
or
always
#5 clk = ~clk;
initial
clk = 0;
Strange code, you are resolving clk drives using an or-gate behaviour. First assign is constantly driving 0. Second assign is inverting the resolved value. But what is the initial value of the second wor input? Wouldn't that second assign produce X in the first place (X ored with 0 would give you X)? Have your tried running it in the simulator or at least drawing somewhere what hardware do you want to get? It's like you're feeding and inverter with 0 or'ed with X which will produce X.
If you want to model a clock you can:
1) convert first assign into initial begin clk = 0; end
2) second assign to always
3) make clk reg type
If you want a synthesizable clock generator you would require a source of oscillations, PLL, etc.
As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:
module Addr_8bit(Clk, Rst, En, LEDOut
);
input Clk;
input Rst;
input En;
output reg [7:0] LEDOut;
always #(posedge Clk or posedge Rst) begin
if(Rst)
LEDOut <= 8'b00000000;
if(En)
LEDOut <= LEDOut + 8'b00000001;
end
endmodule
The error is on the line where the non-blocking assignment: LEDOut <= LEDOut + 8'b00000001; is located.
Particularly it says that:
ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).
Thank You.
Change your behavioral description (the code inside the always block) as follows:
always#(posedge CLK or negedge RST) begin
if(!RST) begin // Reset condition goes here
LEDOut <= 0;
end
else begin // Everything else goes here
if(En)
LEDOut <= LEDOut + 1'b1;
end
end
The reason your code won't synthesize is because you generally can't assign to the same register under the same edge of two different signals. (You can't have your always block trigger on the low to high transition of CLK and RST if you're assigning to a variable in both cases.) So you can't trigger the reset condition on the positive edge of RST, but you can do it on the negative edge. This is due to the way the physical register elements (called flip-flops) are designed.
I'm new to verilog development and am having trouble seeing where I'm going wrong on a relatively simple counter and trigger output type design.
Here's the verilog code
Note the code returns the same result whether or not the reg is declared on the output_signal without the internal_output_buffer
`timescale 1ns / 1ps
module testcounter(
input wire clk,
input wire resetn,
input wire [31:0] num_to_count,
output reg [7:0] output_signal
);
reg [31:0] counter;
initial begin
output_signal = 0;
end
always#(negedge resetn) begin
counter = 0;
end
always#(posedge clk) begin
if (counter == num_to_count) begin
counter = 0;
if (output_signal == 0) begin
output_signal = 8'hff;
end
else begin
output_signal = 8'h00;
end
end
else begin
counter = counter + 1;
end
end
assign output_signal = internal_output_buffer;
endmodule
And the code is tested by
`timescale 1ns / 1ps
module testcounter_testbench(
);
reg clk;
reg resetn;
reg [31:0] num_to_count;
wire [7:0] output_signal;
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
num_to_count = 20;
end
initial begin
#7 resetn = 1;
#35 resetn = 0;
end
testcounter A1(.clk(clk),.resetn(resetn),.num_to_count(num_to_count),.output_signal(output_signal));
endmodule
Behavioral simulation looks as I expected
But the timing simulation explodes
And for good measure: the actual probed execution blows up and looks like
Any tips would be appreciated. Thanks all.
The difference between the timing and functional simulations is that a timing simulation models the actual delay of logic gates while the functional simulation just checks if values are correct.
For e.g. if you have a simple combinational adder with two inputs a and b, and output c. A functional simulation will tell you that c=a+b. and c will change in the exact microsecond that a or b changes.
However, a timing simulation for the same circuit will only show you the result (a+b) on c after some time t, where t is the delay of the adder.
What is your platform? If you are using an FPGA it is very difficult to hit 500 MHz. Your clock statement:
forever #1 clk = ~clk;
shows that you toggle the clock every 1ns, meaning that your period is 2ns and your frequency is 500MHz.
The combinational delay through FPGA resources such as lookup tables, multiplexers and wire segments is probably more than 2ns. So your circuit violates timing constraints and gives wrong behaviour.
The first thing I would try is to use a much lower clock frequency, for example 100 MHz and test the circuit again. I expect it to produce the correct results.
forever #5 clk = ~clk;
Then to know the maximum safe frequency you can run at, look at your compilation reports in your design tools by running timing analysis. It is available in any FPGA CAD tool.
Your code seems working fine using Xilinx Vivado 14.2 but there is only one error which is the following line
assign output_signal = internal_output_buffer;
You can't assign registers by using "assign" and also "internal_output_buffer" is not defined.
I also personally recommend to set all registers to some values at initial. Your variables "resetn" and "counter" are not assigned initially. Basicly change your code like this for example
reg [31:0] counter = 32'b0;
Here is my result with your code:
Your verilog code in the testcounter looks broken: (a) you're having multiple drivers, and (b) like #StrayPointer notices, you're using blocking assignments for assigning Register (Flip-Flop) values.
I'm guessing your intent was the following, which could fix a lot of simulation mismatches:
module testcounter
(
input wire clk,
input wire resetn,
input wire [31:0] num_to_count,
output reg [7:0] output_signal
);
reg [31:0] counter;
always#(posedge clk or negedge resetn) begin
if (!resetn) begin
counter <= 0;
end else begin
if (counter == num_to_count) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
end
assign output_signal = (counter == num_to_count) ? 8'hff : 8'h00;
endmodule
The following code is written for an asynchronous counter. The program compiles fine but the counter value doesn't increment after 1. What am I doing wrong?
Here is the code:
//TOP
module CounterWithDivider(clk,reset,temp,q);
input clk,reset;
output [3:0]q;
output reg [3:0]temp;
reg [3:0]clkDivider;
TFF a(clkDivider,clk,reset,q[0]);
TFF b(clkDivider,q[0],reset,q[1]);
TFF c(clkDivider,q[1],reset,q[2]);
TFF d(clkDivider,q[2],reset,q[3]);
always #(posedge clk or negedge reset)
begin
if(~reset || clkDivider==12)
clkDivider<=0;
else
if(clk)
begin
clkDivider<=clkDivider+1;
temp<=clkDivider;
end
end
endmodule
// T flip flop
module TFF(clkDivider,clk,reset,q);
input clk,reset;
input [3:0]clkDivider;
output reg q;
always #(posedge clk or negedge reset)
begin
if(~reset)
q<=0;
else
if(clkDivider==11)
q<=1;
end
endmodule
A T-FlipFlop, or toggle flop should toggle its output when enabled, you just have:
if(clkDivider==11)
q<=1;
Replace q<=1 with q<=~q to make it toggle when enabled.
As you mentioned, this is an asynchrous counter. The reason your Verilog simulation is not doing what you want is that TFF instance b is trying to sample its data input (clkDivider) using a different clock signal. clkDivider is clocked by signal clk, but you are trying to sample it using a different clock signal (q[0]).
You need to either find a way to synchronize the clkDivider signal into each of the other 3 clock domains, or use a fully synchronous design.