Problem in synthesize Verilog code Sign_Mag adder - verilog

Question

`timescale 1ns / 1ps
module Signadder(
input wire [3:0] a,
input wire [3:0] b,
output reg [3:0] sum
);
reg [2:0] mag_a, mag_b,mag_sum, max, min;
reg sign_a, sign_b, sign_sum;
always #*
begin
mag_a = [2:0]a;
mag_b = [2:0]b;
sign_a = [3]a;
sign_b = [3]b;
if(mag_a>mag_b)
begin
max = mag_a;
min = mag_b;
sign_sum = sign_a;
end
else
begin
max = mag_b;
min = mag_a;
sign_sum = sign_b;
end
if (sign_a == sign_b)
mag_sum = mag_a +mag_b;
else
mag_sum = max - min;
assign sum = {sign_sum,mag_sum};
end
endmodule
I describe a Sign_mag adder with Verilog, but I get these errors when I synthesize:
Line 35: Syntax error near "[".
Line 36: Syntax error near "[".
Line 33: a is not a task
Line 34: b is not a task
I can't find any syntax error in my Verilog code, and with "a is not a task", I fix it by use intermediate register :
reg [3:0] a1;
reg [3:0]b1;
a1 = a;
b1 = b;
But, it still does not work. I hope somebody has any idea why.

Answer 1

The syntax error is due to the following lines:
mag_a = [2:0]a;
mag_b = [2:0]b;
sign_a = [3]a;
sign_b = [3]b;
The signal name should be to the left of the square brackets:
mag_a = a[2:0];
mag_b = b[2:0];
sign_a = a[3];
sign_b = b[3];
In addition to that, you are not following good coding practices for synthesizable code.
You should not use the assign keyword inside an always block.
You have combinational feedback loops inside your always block. You should not read from and assign to the same signal. For example, mag_a:
mag_a = a[2:0];
max = mag_a;