module booth(num1,num2,prod);
input [22:0] num1,num2;
output [45:0] prod;
reg [22:0]num1_bar;
reg [46:0]sub_1;
reg [22:0]temp;
reg [22:0]result;
reg [1:0]sel;
reg [22:0]add;
reg [22:0]zeros;
assign temp = ~ num1;
assign num1_bar = temp + "00000000000000000000001";
assign sub_1 = {zeros[22:0], num2, "0"};
integer i;
always #* begin
for( i = 0; i < 22; i = i+1) begin
assign sel = sub_1[1:0];
if(sel == "10") begin
assign add = sub_1[46:24] + num1_bar;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
elseif(sel == "01") begin
assign add = sub_1[46:24] + num1 ;
assign sub_1 ={add[22],add,sub_1[23:1]};
end
else begin
assign sub_1= {sub_1[46] ,sub_1[46:1]};
end
end
endmodule
I am trying to implement a floating point multiplier using carry look ahead adder and booth multiplier. After running the above code following errors has occurred only for the booth multiplier.
Please help me out.
ERRORS:
Summary Tue Apr 7 15:25:28 2015
Summary New
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 45. Syntax error near "begin".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 49. Syntax error near "else".
ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 54. Syntax error near "endmodule".
INFO ProjectMgmt:1845 - Analyzing Verilog file "D:/XILINX PROGRAM/bth/booth.v" into library work
You seem to have a confusion between VHDL and Verilog.
Vector constants in Verilog are in the form: Y'zXXXXXXX where Y is the number of bits of the vector, z is the base (b for binary, d for decimal, h for hexadecimal), and XXXX is the constante value in the specified base.
else if must separated
For example, the line:
if(sel == "10") begin
Must be rewritten as:
if(sel == 2'b10) begin
For large vectors, you can ommit the size specifier, and write the constant as this:
assign num1_bar = temp + 'b00000000000000000000001;
You are missing an end matching the begin of the always block.
(Once you have fixed that, you will see that there are other errors, too. See mcleod_ideafix's answer.)
Related
`timescale 1ns / 1ps
module Signadder(
input wire [3:0] a,
input wire [3:0] b,
output reg [3:0] sum
);
reg [2:0] mag_a, mag_b,mag_sum, max, min;
reg sign_a, sign_b, sign_sum;
always #*
begin
mag_a = [2:0]a;
mag_b = [2:0]b;
sign_a = [3]a;
sign_b = [3]b;
if(mag_a>mag_b)
begin
max = mag_a;
min = mag_b;
sign_sum = sign_a;
end
else
begin
max = mag_b;
min = mag_a;
sign_sum = sign_b;
end
if (sign_a == sign_b)
mag_sum = mag_a +mag_b;
else
mag_sum = max - min;
assign sum = {sign_sum,mag_sum};
end
endmodule
I describe a Sign_mag adder with Verilog, but I get these errors when I synthesize:
Line 35: Syntax error near "[".
Line 36: Syntax error near "[".
Line 33: a is not a task
Line 34: b is not a task
I can't find any syntax error in my Verilog code, and with "a is not a task", I fix it by use intermediate register :
reg [3:0] a1;
reg [3:0]b1;
a1 = a;
b1 = b;
But, it still does not work. I hope somebody has any idea why.
The syntax error is due to the following lines:
mag_a = [2:0]a;
mag_b = [2:0]b;
sign_a = [3]a;
sign_b = [3]b;
The signal name should be to the left of the square brackets:
mag_a = a[2:0];
mag_b = b[2:0];
sign_a = a[3];
sign_b = b[3];
In addition to that, you are not following good coding practices for synthesizable code.
You should not use the assign keyword inside an always block.
You have combinational feedback loops inside your always block. You should not read from and assign to the same signal. For example, mag_a:
mag_a = a[2:0];
max = mag_a;
I am wondering if it is possible in verilog to create an n-bit carry lookahead adder. With some help from the comments I've been able to come this far
module nbit_lookahead(x, y, cin, cout, s);
parameter n = 1;
integer i;
integer j;
input wire [n:0] x, y, cin;
output wire [n:0] cout, s;
wire [n:0] g, p;
reg cpp, gp;
generate
cpp = 1; // ERROR HERE -- Line 25
gpp = 1;
for(i = 0; i < n; i=i+1) begin : outer_loop
assign p[i] = x[i] | y[i];
assign g[i] = x[i] & y[i];
assign s[i] = cin[i]^x[i]^y[i];
for(j = i - 1; j >= 0; j=j-1) begin : inner_loop
cpp &= (cin[j] & p[j] & p[i]); // ERROR HERE -- Line 32
gp &= (g[j] & p[i]) & gp;
end
assign cout[n] = cpp | gp | (x[i] & y[i]);
end
endgenerate
endmodule
The challenge I'm having now is how to assign cpp and gp. I keep getting errors:
Error (10170): Verilog HDL syntax error at fourbit_lookahead.v(25) near text: "="; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword.
Error (10170): Verilog HDL syntax error at fourbit_lookahead.v(32) near text: "&"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword.
I'm pretty rusty, but mixing wires and regs looks wrong to me in the for loop. The first thing I would try here is to make cpp and gpp bit vectors, so that everything is parallel. That way you don't have any reassignments in the inner loop. In generate, your have cpp[0]=1'b1, and gpp[0]=1'b1, then in the inner loop, assign cpp[i+1] and gpp[i+1] to your value. It also looks wrong to be setting cout[n] inside every iteration of the loop. You should be setting cout[i] based on cpp[i] and gpp[i].
In the following Verilog module, I'd like to understand why the blocking assignment using concatenation doesn't give the same result as the 2 commented out blocking assignments.
When I run the program on the FPGA, it gives the expected result with the 2 blocking assignments (the leds blink), but not with the blocking assignment using concatenation (the leds stay off).
Bonus points for answers pointing to the Verilog specification explaining what is at play here!
/* Every second, the set of leds that are lit will change */
module blinky(
input clk,
output [3:0] led
);
reg [3:0] count = 0;
reg [27:0] i = 0;
localparam [27:0] nTicksPerSecond = 100000000;
assign led = {count[3],count[2],count[1],count[0]};
always # (posedge(clk)) begin
// This works:
//count = i==nTicksPerSecond ? (count + 1) : count;
//i = i==nTicksPerSecond ? 0 : i+1;
// But this doesn't:
{count,i} = i==nTicksPerSecond ?
{count+1, 28'b0 } :
{count , i+1};
end
endmodule
PS: I use Vivado 2018.2
The reason is because the widths of count+1 and i+1 are both 32 bits. An unsized number is 32 bits wide (1800-2017 LRM section 5.7.1) and the width of the addition operator is the size of the largest operand (LRM section 11.6.1). To make your code work, add a proper size to your numeric literals
{count,i} = i==nTicksPerSecond ?
{count+4'd1, 28'b0 } :
{count , i+28'd1};
A simpler way to write this code is
always # (posedge clk)
if (i== nTicksPerSecond)
begin
count <= count + 1;
i <= 0;
end
else
begin
i <= i + 1;
end
I am trying to implement the circuit mentioned at this question: How to perform right shifting binary multiplication?
I am getting the error:
Error (10170): Verilog HDL syntax error at mult.v(9) near text "="; expecting ".", or an identifier, or "["
I tried to Google it, but I couldn't find anything
Code:
module mult (multiplier, multiplicand, result, clk);
input [3:0] multiplier;
input [4:0] multiplicand;
input clk;
output [8:0] result;
reg [8:0] product;
initial
begin
product [8:4] = 4'b00000;
product [3:0] = multiplier [3:0];
end
assign result = product;
always # (posedge clk)
begin
if (product[0] == 1)
begin
product = product >> 1; // shift right, and assign the most significant bit to 0
product[8:4] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out
end
else
begin
product = product >> 1; // shift to the right
end
end
endmodule
The reason for your syntax error is that you cannot just write:
product [7:4] = 4'b0000;
you must write
assign product [7:4] = 4'b0000;
But, unless you are using System-Verilog (and your old-fashioned style of coding suggests you are not), you will find that
assign product [7:4] = 4'b0000;
will not compile either, because the target of an assign statement must be a wire, not a reg. And if you change product to a wire, you will then find these statements give you and error:
product = product >> 1; // shift right, and assign the most significant bit to 0
product[7:3] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out
and
product = product >> 1; // shift to the right
because you cannot assign to a wire in an always (or initial) block.
You seem to be designing some kind of shift-and-add multiplier and presumably want to initialise product at the beginning of the calculation. (Assuming you sort the syntax) the lines
(assign) product [7:4] = 4'b0000;
(assign) product [3:0] = multiplier [3:0];
drive product continuously, for all time; they do not initialise product. You are designing hardware here, not writing software.
I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it straight.
MAIN FILE
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
RANDOM NUMBER GENERATOR
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff #(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
HERE'S THE IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
LOGS
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
There are a lot of things wrong here.
The most important problem, though, is that you are trying to write Verilog code as if it's a procedural programming language. This won't work; Verilog is a hardware description language. You cannot use constructs like for and while loops to implement iteration in hardware; these operations must be implemented as clocked logic.
Get a good textbook on FPGA design and work through it. You have a lot to learn.
If this is coursework: contact your professor or a teaching assistant now. You are not going to make your deadline.