I am kinda new to verilog and struggling with all the basic concepts.
I am trying to display the timing waveform in ModelSim, where is simply throws "# (vish-4014) No objects found matching '/tb/*'. "(in my case).
Whereas when I simulate the testbench in VSCode, using icarus & gkwave, it displays the necessary waveforms I require. In VS Code, I run
iverilog -o tb.vvp tb.v
vvp tb.vvp
gtkave
GTKwave pops up and shows the waveforms. The hardware I am testing out takes 2 numbers as inputs and returns the small and large number (cnsmodule attached below). The testbench I am simulating is named "tb.v" and goes as:
module tb();
reg a0,a1,a2,a3;
wire s0,s1,s2,s3;
level uu(.*);
always begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
a0=2'b01;a1=2'b00;a2=2'b11;a3=2'b10;
#10;
$finish;
end
endmodule
The relevant modules I am instantiating are:
// Instantiates 3 cnsmodules to input 4 numbers and return them from small to large
module level(a0,a1,a2,a3,s0,s1,s2,s3);
input a0,a1,a2,a3;
output s0,s1,s2,s3;
wire s0,s1,s2,s3;
wire temp1,temp2;
cnsmodule tvz1(a0,a1,s0,temp1);
cnsmodule tvz2(temp1,a2,s1,temp2);
cnsmodule tvz3(temp2,a3,s2,s3);
endmodule
and:
module cnsmodule (a0,a1,sn,ln);
input a0,a1;
output sn,ln;
reg sn,ln;
always#(*) begin
if (a0>a1) begin
sn=a1; ln=a0;
end
else begin
sn=a0; ln=a1;
end
end
endmodule
I suspect that your problem lies with the optimization ModelSIM does to the design, Try the following and tell me if that works in the top bar click on simulate and then followed by optimization options and then click on "Apply full visibillity to all modules(full debug mode)" and then choose your testbench and try to add your signals now
Related
I have two test benches:
// test_a.v
module test_a;
initial
begin
for (int i = 0; i < 128; i++) begin
$display("hello");
#10;
end
end
endmodule
// test_b.v
module test_b;
initial
begin
#50;
$finish();
end
endmodule
I build and run this like so:
iverilog -g2012 -o icarus.out test_a.v test_b.v
vvp icarus.out
...and then see this output:
hello
hello
hello
hello
hello
hello
But it stops there. Why do I not get 128 "hello"s? I guess the $finish() in test_b.v causes test_a.v to quit early but is that expected?
https://www.edaplayground.com/x/JjJR
Most likely a problem with a piece of code you have not shown. Adding a final block after the initial block might give some clues.
final $display($realtime);
It is unfortunate that Icarus Verilog does not notify you that it has hit a $finish and just prints Done. So you might wanna search for other $finish tasks and put a $display statement just before it.
UPDATE:
Based on your updated code, all modules share the same global concept of simulation time, beginning and end-of-time. When one module executes a $finish, that is the end-of-time for the entire simulation. The way you have coded it, there is a race condition whether you would see 5 or 6 "hello"s.
My code is:
module circuilar_fifo;
localparam B=3,W=2;
input wire clk,reset,wr,rd;
input wire [B-1:0] wr_data;
output wire [B-1:0] rd_data;
output wire full,empty;
Isn't this one of the correct method of declaring input outputs? But why does the Xilinx vivado 2017.4 webpack edition is showing that
port rd_data is not defined
Why is it showing like this? Where am I went wrong? I could've designed the code in
module circular_fifo(
input wire [B-1:0] wr_data;
input wire clk,reset
............
);
But what is wrong in 1st coding design?
In the first style, the module header needs a list of port names thus:
module circular_fifo(clk, reset, wr, rd, rd_data, wr_data, full, empty);
I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number.
Here is my code:
module ProjectDSD(alteraClock, sensorInput, openValve);
input sensorInput, alteraClock;
output openValve;
always #(sensorInput)
begin
if(sensorInput < 100) //sensor value to irrigate at
begin
openValve <= 1; //here
end
else
begin
openValve <= 0; //here
end
end
endmodule
Im getting an error saying:
Object "openValve" on left-hand side of assignment must have a variable data type
What am I missing? Also, which pins can I use on an Altera DE2-155 board to output a digital signal of only 1's and 0's for the the valve to open/close?
s/output openValve/output reg openValve/
Outputs default to wire; you need a reg. See also this question.
openValve is currently inferred as a wire. Add reg openValve; below output openValve; and your code will work.
Suggestions: It looks like you are following the IEEE1364-1995 non-ANSI coding style. Will still legal, you might want to change to the ANSI coding style, supported in IEEE1364-2001 and above.
Non-ANSI:
module ProjectDSD(alteraClock, sensorInput, openValve);
input sensorInput, alteraClock;
output openValve;
reg openValve;
ANSI:
module ProjectDSD(
input alteraClock, sensorInput,
output reg openValve);
For combinational blocks, it is recommended to use always #* (or the synonymous always #(*)) instead of always #(sensorInput). #* is an auto sensitivity list also added in IEEE1364-2001
Try output reg openValve;.
For the second half of your question (which should really be a separate question) import this QSF file into your project. Any of the GPIO can be configured as outputs, and are accessible by the 40-pin header on the side.
I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile > Compile All), I'm typing vsim into the console, and the only error thrown is
# vsim
# Start time: [time]
# Error loading design
Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong?
For reference, my code is below:
methods.v
module dFlipFlop(
D,
Clk,
En,
Q
);
input D, Clk, En;
output Q;
reg Q;
always # (posedge Clk)
if(~En) begin
Q <= 1'b0;
end else begin
Q <= D;
end
endmodule
module masterSlaveDFF(
D,
Clk,
En,
Q
);
input D, Clk, En;
output Q;
wire Y, inClk;
assign inClk = ~Clk;
dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y));
dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q));
endmodule
dflipflop.v (My Testbench)
`include "methods.v"
module masterSlaveTest();
reg D, Clk, En, Q;
initial begin
$monitor(D, Clk, En, Q);
D = 1;
Clk = 1;
En = 0;
#5 $finish;
end
always begin
#5 Clk = ~Clk;
end
endmodule
If your code compiles, and directly invoking a test bench doesn't work, aka via something like
vsim -novopt [your testbench module name here]
or just
vsim
Then, at least in my case, it was a problem of licensing. Note that I am using the Student Edition of ModelSim. When I first ran vsim it gave a long error message explaining that I needed to put the License file (which you get during the installation) in a certain directory.
For the Student Edition, you must rename the file student_license.dat to license.dat and place it in C:\Modeltech_pe_edu_10.4a\win32pe_edu\. Your directory structure may vary, but as I understand the naming conventions are similar.
In some cases I also read that the license.dat needs to be in the parent file of win32pe_edu, but in my case, it worked in win32pe_edu.
To the Windows users:
If your code is correct and you already copied your license file (student_license.dat) in the correct folder (C:\Modeltech_pe_edu_[VersionNo]) and it still does not work try to run ModelSim as administrator. This might do the trick.
I had the same issue. I resolved it by right clicking on the specific library and clicking "refresh". Then, I recompiled and restarted simulation, and it worked.
I had the same problem . This is how I fixed it. When I installed modelsim, in the end it directs me to a license key page! I filled it but did not receive an email!
So if you don't receive a mail containing the license key from modelsim then you will have to re-run the installation all over again! So once you receive the license_file.dat, paste it in the modelsim folder, then you will not face any such problems!
for me the problem was with optimization, when i started simulation with optimization ON, it didnt show created instances in testbench, and by turning it off i get the "Error Loading Design" error.
How i fix it:
in gui:
simulate > start simulation > optimization option > in the visibility tab> check the "apply full visibility to all modules(full debug mode)" .
in terminal:
vsim -gui -vopt -voptargs=+acc work.Adder_TB
(Adder_TB is my testbench module name) .
I have created two different Verilog Modules (shiftByImm and immShifter). What I want to do is to select only the output of one of the two as the output of this little multiplexer module I am creating.
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
shiftByImm shift0(in, shift_value, shift, out);
immShifter shift1(in, shift_value, out);
assign {out} = select == 1'b0 ? shift0 : shift1;
endmodule
However, this gives me two perfectly understandable errors:
Illegal reference to interface "shift0"andIllegal reference to interface "shift1"
I know that there is something missing here. How do I select the output of the SuperShifter module to be the same output of one of the pre-made modules?
You're issue is with your naming conventions. You have 2 modules (I'm guessing) with 2 different outputs, but you give them the same name. In this example, you are using the port order method. The names in the parentheses are associated implicitly by order and do not need to be the same as what they are inside the instantiation. The other way is to connect the ports by name. In the example I show both methods. From that point, you would have to use the wires declared to choose an output with your "little mux".
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
wire [0:31] temp_out_0;
wire [0:31] temp_out_1;
shiftByImm shift0(in, shift_value, shift, temp_out_0);
immShifter shift1(.in(in), .shift_value(shift_value), .out(temp_out_1));
assign {out} = select == 1'b0 ? temp_out_0 : temp_out_1;
endmodule
Following on from #N8TROs answer it looks like you are trying to 'call' the modules and have them generate the output.
Modules are not equivalent to tasks which are called when required they represent physical blocks of hardware. The mux needs to select the output which you want not the module you wish to be active.
As you have both modules driving the same output you will likely see xs When one module drives 1 and the other 0 the wire or net will end up in conflict.
I really agree with N8TROs recommendation to use ANSI style named ports, this really helkps debugging and code maintenance.
but for brevity and to see minimal changes in the code to make it work:
shiftByImm shift0(in, shift_value, shift, out0); //<-- Unique output
immShifter shift1(in, shift_value, out1); //<-- Unique output
assign {out} = select == 1'b0 ? out0: out1; //<-- select output