Verilog: Select one of two instances as the Output - verilog

Question

I have created two different Verilog Modules (shiftByImm and immShifter). What I want to do is to select only the output of one of the two as the output of this little multiplexer module I am creating.
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
shiftByImm shift0(in, shift_value, shift, out);
immShifter shift1(in, shift_value, out);
assign {out} = select == 1'b0 ? shift0 : shift1;
endmodule
However, this gives me two perfectly understandable errors:
Illegal reference to interface "shift0"andIllegal reference to interface "shift1"
I know that there is something missing here. How do I select the output of the SuperShifter module to be the same output of one of the pre-made modules?

Answer 1

You're issue is with your naming conventions. You have 2 modules (I'm guessing) with 2 different outputs, but you give them the same name. In this example, you are using the port order method. The names in the parentheses are associated implicitly by order and do not need to be the same as what they are inside the instantiation. The other way is to connect the ports by name. In the example I show both methods. From that point, you would have to use the wires declared to choose an output with your "little mux".
module superShifter(input [0:31] in, input select, input [0:4] shift_value, input[0:1] shift, output reg [0:31] out);
wire [0:31] temp_out_0;
wire [0:31] temp_out_1;
shiftByImm shift0(in, shift_value, shift, temp_out_0);
immShifter shift1(.in(in), .shift_value(shift_value), .out(temp_out_1));
assign {out} = select == 1'b0 ? temp_out_0 : temp_out_1;
endmodule

Answer 2

Following on from #N8TROs answer it looks like you are trying to 'call' the modules and have them generate the output.
Modules are not equivalent to tasks which are called when required they represent physical blocks of hardware. The mux needs to select the output which you want not the module you wish to be active.
As you have both modules driving the same output you will likely see xs When one module drives 1 and the other 0 the wire or net will end up in conflict.
I really agree with N8TROs recommendation to use ANSI style named ports, this really helkps debugging and code maintenance.
but for brevity and to see minimal changes in the code to make it work:
shiftByImm shift0(in, shift_value, shift, out0); //<-- Unique output
immShifter shift1(in, shift_value, out1); //<-- Unique output
assign {out} = select == 1'b0 ? out0: out1; //<-- select output