How to return an array in systemVerilog - verilog

I am having some issues returning an array from a function in systemVerilog. However, I keep having a syntax error. I am not sure if referencing an array works here since I need to send args to my function.
Code :
module VGA_Setup
(
input wire clk, reset,
output wire hsync, vsync,
output wire [3:0] r, g, b
);
// constant declarations for VGA sync parameters
localparam H_DISPLAY = 640; // horizontal display area
localparam H_L_BORDER = 48; // horizontal left border
localparam H_R_BORDER = 16; // horizontal right border
localparam H_RETRACE = 96; // horizontal retrace
localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
localparam V_DISPLAY = 480; // vertical display area
localparam V_T_BORDER = 10; // vertical top border
localparam V_B_BORDER = 33; // vertical bottom border
localparam V_RETRACE = 2; // vertical retrace
localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
int sq_pix = 80;
wire video_on, p_tick;
int colours [3];
reg [3:0] red_reg, green_reg, blue_reg;
reg [11:0] rbg;
// mod-2 counter to generate 25 MHz pixel tick
reg pixel_reg = 0;
wire pixel_next;
wire pixel_tick;
always #(posedge clk)
pixel_reg <= pixel_next;
assign pixel_next = ~pixel_reg; // next state is complement of current
assign pixel_tick = (pixel_reg == 0); // assert tick half of the time
// registers to keep track of current pixel location
reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
// register to keep track of vsync and hsync signal states
reg vsync_reg, hsync_reg;
wire vsync_next, hsync_next;
// infer registers
always #(posedge clk)
if(~reset)
begin
v_count_reg <= 0;
h_count_reg <= 0;
vsync_reg <= 0;
hsync_reg <= 0;
end
else
begin
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
end
// next-state logic of horizontal vertical sync counters
always #*
begin
h_count_next = pixel_tick ?
h_count_reg == H_MAX ? 0 : h_count_reg + 1
: h_count_reg;
v_count_next = pixel_tick && h_count_reg == H_MAX ?
(v_count_reg == V_MAX ? 0 : v_count_reg + 1)
: v_count_reg;
end
// hsync and vsync are active low signals
// hsync signal asserted during horizontal retrace
assign hsync_next = h_count_reg >= START_H_RETRACE
&& h_count_reg <= END_H_RETRACE;
// vsync signal asserted during vertical retrace
assign vsync_next = v_count_reg >= START_V_RETRACE
&& v_count_reg <= END_V_RETRACE;
// video only on when pixels are in both horizontal and vertical display region
assign video_on = (h_count_reg < H_DISPLAY)
&& (v_count_reg < V_DISPLAY);
// output signals
assign hsync = hsync_reg;
assign vsync = vsync_reg;
assign p_tick = pixel_tick;
colours = Letter_J(h_count_reg,v_count_reg);
// output
assign r = (video_on) ? colours[0] : 4'b0;
assign g = (video_on) ? colours[1] : 4'b0;
assign b = (video_on) ? colours[2] : 4'b0;
endmodule
function int[] Letter_J (int h_count_reg, int v_count_reg);
int colours_red = 0;
int colours_green = 0;
int colours_blue = 0;
int colours [3];
if ((h_count_reg > 160) && (h_count_reg < 400)) begin
if ((h_count_reg > 240) && (h_count_reg < 320)) begin
if ((v_count_reg > 80) && (v_count_reg < 240)) begin
colours_red = 4'b1111;
colours_green = 4'b1111;
colours_blue = 4'b1111;
end
end
end else begin
colours_red = 4'b0000;
colours_green = 4'b0000;
colours_blue = 4'b0000;
end
colours [0] = colours_red;
colours [1] = colours_green;
colours [2] = colours_blue;
return colours;
endfunction
Error :
Error (10170): Verilog HDL syntax error at VGA_Setup.sv(108) near text: "="; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword...
Thank you for your help.
Joe

The SystemVerilog BNF requires that you use a typedef for the return type of a function when that type is an aggregate. So you must do:
typedef int intDA_t[];
function intDA_t Letter_J (int h_count_reg, int v_count_reg);

Related

Register and integer comparison does not work

I am facing an interesting issue in SystemVerilog where the comparison with a register isn't working.
module VGA_Colours
(
input wire clk, reset,
// input wire [3:0] swred, swgreen,
// input wire [1:0] swblue,
output wire hsync, vsync,
output wire [3:0] r, g, b
);
// constant declarations for VGA sync parameters
localparam H_DISPLAY = 640; // horizontal display area
localparam H_L_BORDER = 48; // horizontal left border
localparam H_R_BORDER = 16; // horizontal right border
localparam H_RETRACE = 96; // horizontal retrace
localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
localparam V_DISPLAY = 480; // vertical display area
localparam V_T_BORDER = 10; // vertical top border
localparam V_B_BORDER = 33; // vertical bottom border
localparam V_RETRACE = 2; // vertical retrace
localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
wire video_on, p_tick;
reg [9:0] ii;
reg j;
reg [3:0] red_reg, green_reg, blue_reg;
reg [11:0] rbg;
// mod-2 counter to generate 25 MHz pixel tick
reg pixel_reg = 0;
wire pixel_next;
wire pixel_tick;
always #(posedge clk)
pixel_reg <= pixel_next;
assign pixel_next = ~pixel_reg; // next state is complement of current
assign pixel_tick = (pixel_reg == 0); // assert tick half of the time
// registers to keep track of current pixel location
reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
// register to keep track of vsync and hsync signal states
reg vsync_reg, hsync_reg;
wire vsync_next, hsync_next;
// infer registers
always #(posedge clk)
if(~reset)
begin
v_count_reg <= 0;
h_count_reg <= 0;
vsync_reg <= 0;
hsync_reg <= 0;
end
else
begin
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
end
// next-state logic of horizontal vertical sync counters
always #*
begin
h_count_next = pixel_tick ?
h_count_reg == H_MAX ? 0 : h_count_reg + 1
: h_count_reg;
v_count_next = pixel_tick && h_count_reg == H_MAX ?
(v_count_reg == V_MAX ? 0 : v_count_reg + 1)
: v_count_reg;
end
// hsync and vsync are active low signals
// hsync signal asserted during horizontal retrace
assign hsync_next = h_count_reg >= START_H_RETRACE
&& h_count_reg <= END_H_RETRACE;
// vsync signal asserted during vertical retrace
assign vsync_next = v_count_reg >= START_V_RETRACE
&& v_count_reg <= END_V_RETRACE;
// video only on when pixels are in both horizontal and vertical display region
assign video_on = (h_count_reg < H_DISPLAY)
&& (v_count_reg < V_DISPLAY);
// output signals
assign hsync = hsync_reg;
assign vsync = vsync_reg;
assign p_tick = pixel_tick;
always #(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
ii <= ii + 9'b001010000;
rbg <= rbg + 12'b000010000000;
end
end
end
// output
assign r = (video_on) ? rbg[11:8] : 4'b0;
assign g = (video_on) ? rbg[7:4] : 4'b0;
assign b = (video_on) ? rbg[3:0] : 4'b0;
endmodule
In the above code h_count_reg is 0 works fine. If I change 0 to any different number, it will work as expected. However, if I replace that number with a variable (which is "ii", declared on top of my module as reg[9:0] ii), the code seems to ignore it, which is weird. Replacing the ii variable with any number will work. Why?
TestBench file:
module VGA_Colours_tb ();
logic clk;
reg reset;
wire hsync, vsync;
wire [3:0] r, g, b;
VGA_Colours scr0 (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.r (r),
.b (b),
.g (g)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
always #(posedge clk) begin
#20
reset <= 1'b0;
#20
reset <= 1'b1;
#100000
$finish;
end
endmodule
Simulation wave:
As you can see from the code, when h_count_reg is == to ii, increment the rbg and the value of ii. However, based on the simulation waves, it is not doing that as if the value of h_count_reg is not equal to ii while it actually is.
You have a logic error in the VGA_Colours module.
Here is your code with more consistent indentation:
always #(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
rbg <= rbg + 12'b000010000000;
ii <= ii + 9'b001010000;
end
end
end
When I run your simulation, I observe ii is always 0 after the initial reset.
The code has 3 if statements. The 1st if statement is true at the beginning of the simulation, when reset=0. This sets ii to 0.
After reset, I see h_count_reg=0 4 times. This means the 2nd if statement is true 4 times. This keeps ii = 0.
The 3rd if statement is evaluated only when h_count_reg is not 0. It should be clear now that the 3rd if statement can never be true. This means that ii will not be incremented and it will remain at 0. For example, when h_count_reg=1, then (h_count_reg == ii) is false because ii is always 0.

Verilog can't figure out why a reg is always X

I am trying to do a VGA output using verilog but I can't seem to figure out why r_hcount stays X. The simulation waveforms show that r_vcount is being reset to 0 properly but for some reason r_hcount never gets reset to 0. I can't figure out why...
Verilog code:
module m_VGA640x480(
input wire iw_clock,
input wire iw_pix_stb,
input wire iw_rst,
output wire ow_hs,
output wire ow_vs,
output wire ow_blanking,
output wire ow_active,
output wire ow_screenend,
output wire ow_animate,
output wire [9:0] ow_x,
output wire [9:0] ow_y
);
localparam HS_STA = 16;
localparam HS_END = 16 + 96;
localparam HA_STA = 16 + 96 + 48;
localparam VS_STA = 480 + 11;
localparam VS_END = 400 + 11 + 2;
localparam VA_END = 480;
localparam LINE = 800;
localparam SCREEN = 524;
reg [9:0] r_hcount;
reg [9:0] r_vcount;
assign ow_hs = ~((r_hcount >= HS_STA) & (r_hcount < HS_END));
assign ow_vs = ~((r_vcount >= VS_STA) & (r_vcount < VS_END));
assign ow_x = (r_hcount < HA_STA) ? 0 : (r_hcount - HA_STA);
assign ow_y = (r_vcount >= VA_END) ? (VA_END - 1) : (r_vcount);
assign ow_blanking = ((r_hcount < HA_STA) | (r_vcount > VA_END - 1));
assign ow_active = ~((r_hcount < HA_STA) | (r_vcount > VA_END - 1));
assign ow_screenend = ((r_vcount == SCREEN - 1) & (r_hcount == LINE));
assign ow_animate = ((r_vcount ==VA_END - 1) & (r_hcount == LINE));
always #(posedge iw_clock)
begin
if (iw_rst)
begin
r_hcount <= 0;
r_vcount <= 0;
end
if (iw_pix_stb)
begin
if (r_hcount == LINE)
begin
r_hcount <= 0;
r_vcount <= r_vcount + 1;
end
else
r_hcount <= r_hcount + 1;
if (r_vcount == SCREEN)
r_vcount <= 0;
end
end
endmodule
Here is the result of the simulation. r_hcount is bugged... The code is supposed to set both counters to 0 when reset is 1 but for some reason it's not getting reset to 0. Please help.
Wavefrorm
From your work, I notice one point may cause the issue
always #(posedge iw_clock)
begin
if (iw_rst)
//you define r_hcount <= 0 here
.....
if (iw_pix_stb) //<== another condition
// r_hcount <= 0 is also defined here
So if posedge clock happened, r_hcount may be bugged here.
I suggest it should be done like this
else if (iw_pix_stb) <=== else if here
Good luck.
After tinkering a bit more with the code, I found out that it was because r_hcount <= 0 was getting overridden by r_hcount <= r_hcount + 1 which will set r_hcount to X. This was caused because the two clock inputs were both the same frequency.
I should be more careful in the future...

Query : No display on monitor ( VGA CONTROLLER 800*600 resolution ) BASYS 2 BOARD

I have created this code for vga controller and the simulation is proper too. The problem is the monitor is blank when code runs, also in the waveform generation the two output's hsync and vsync are displayed '0'. I have no idea where the logic goes wrong. Please help.
Code :
module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);
// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 56; // front porch (right border)
localparam HB = 64; //right porch (left border)
localparam HR = 120; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 37; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 6; // vertical retrace
//horizontal and vertical counter
reg [9:0] h_count = 0;
reg [9:0] v_count = 0;
wire [9:0] h_end,v_end;
assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;
always #(*) begin
if(clk)
if(h_end)
h_count = 0;
else
h_count = h_count+1;
else
h_count = h_count;
end
always #(posedge clk) begin
if(h_end)
if(v_count<v_end)
v_count = v_count+1;
else
v_count = 0;
else
v_count = v_count;
end
assign hsynch = ((h_count >= HD+HF-1) && (h_count <= HD+HF+HR+HB-1));
assign vsynch = ((v_count >= VD+VF-1) && (v_count <= VD+VF+VR+VB-1));
assign video_on = ((h_count < HD) && (v_count < VD));
wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 10'b0;
assign pixel_y = (video_on)? v_count : 10'b0;
reg [7:0] coloroutput;
always #(clk)
if(~video_on)
coloroutput <= 0;
else begin
if( pixel_x<150 && pixel_y<160)
coloroutput[7:5] <= 3'b111;
else if(pixel_x<250 && pixel_y<320)
coloroutput[4:2] <= 3'b111;
else
coloroutput[1:0] <= 2'b11;
end
assign red = (video_on) ? coloroutput[7:5] : 3'b000;
assign green = (video_on) ? coloroutput[4:2] : 3'b000;
assign blue = (video_on) ? coloroutput[1:0] : 3'b000;
endmodule
You should definitely try simulating this. I'm pretty sure you'll find that your code doesn't work in simulation. Always check your code in a simulation environment before trying to program your FPGA! You have this line:
always #(*) begin
if(clk)
if(h_end)
h_count = 0;
h_end is a static value, you need to be comparing it to something. Maybe:
if (h_count == h_end)
something like that. Additionally, this always block should tell the tools to look for a rising edge on your clock signal. E.g.
always #(posedge clk) begin
if (h_count == h_end)

Query : Error in clock divider used in VGA Controller (Verilog) Basys 2 board

I am getting an error while incorporating clock divider ( 40 MHz ) in my VGA Controller (Basys 2 board ). Error in my coding is - Port I of input buffer instance_name/CLKIN_IBUFG_INST is connected to GND.
Please help in removing this error !
Code is as follows :
module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);
// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 40; // front porch (right border)
localparam HB = 88; //right porch (left border)
localparam HR = 128; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 1; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 4; // vertical retrace
wire pixel_tick;
//clock divider
// Instantiate the module
clkdiv instance_name (
.CLKIN_IN(CLKIN_IN),
.RST_IN(RST_IN),
.CLKFX_OUT(pixel_tick),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(LOCKED_OUT)
);
//horizontal and vertical counter
reg [9:0] h_count = 0;
reg [9:0] v_count = 0;
wire [9:0] h_end,v_end;
assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;
always #(pixel_tick)
if(h_count<h_end)
h_count <= h_count+1;
else
h_count <= 0;
always #(*)
if(pixel_tick & h_end)
if(v_count<v_end)
v_count <= v_count+1;
else
v_count <= 0;
else
v_count <= v_count;
assign hsynch = ((h_count>= HD+HF-1) && (h_count<=HD+HF+HR+HB-1));
assign vsynch = ((v_count>=VD+VF-1) && (v_count<= VD+VF+VR+VB-1));
assign video_on = ((h_count <HD) && (v_count<VD));
wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 'b0;
assign pixel_y = (video_on)? v_count : 'b0;
reg [7:0] coloroutput;
always #(pixel_tick)
if(~video_on)
coloroutput <= 0;
else
begin
if(pixel_y<160)
coloroutput[7:5] <= 3'b111;
else if(pixel_y<320)
coloroutput[4:2] <= 3'b111;
else
coloroutput[1:0] <= 2'b11;
end
assign red = (video_on)?coloroutput[7:5] : 3'b000;
assign green = (video_on)?coloroutput[4:2] : 3'b000;
assign blue = (video_on)?coloroutput[1:0] : 3'b000;
endmodule
Searching your code for CLKIN_IN it only appears on the following line, which means there is nothing driving it ie connected to ground (GND).
// Instantiate the module
clkdiv instance_name (
.CLKIN_IN(CLKIN_IN), //<-- Not connected
If variables are not declared logic/wire/reg/tri etc then a 1 bit wire is implied so you do not get the type checking of an unconnected port, it is however un-driven. Simulation should show this as a Z driving in.

Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks
`timescale 1ns / 1ps
module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP);
//USED FOR SEVEN SEG
input clock;
output AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP;
reg [7:0] cathodedata; //cathode data
reg [3:0] anodedata; //anode data
reg [2:0] digit = 1;
reg [6:0] data;
reg setdp;
reg [19:0] counter = 0;
assign CA = cathodedata [7];
assign CB = cathodedata [6];
assign CC = cathodedata [5];
assign CD = cathodedata [4];
assign CE = cathodedata [3];
assign CF = cathodedata [2];
assign CG = cathodedata [1];
assign CDP = cathodedata [0];
assign AN3 = anodedata [3];
assign AN2 = anodedata [2];
assign AN1 = anodedata [1];
assign AN0 = anodedata [0];
//USED FOR SEVEN SEG
//Multiplexing
//Board Clock: 50MHz
//p = t*f
//t = 16ms
//p = 16ms * 50*10^6 = 800,000 cycles
//200,000 cycles for each digit
//Refreshed every 16ms (~60Hz)
always#(negedge clock)
begin
if (digit == 1)
begin
if (counter == 200_000)
begin
digit = 2;
end
else
begin
counter = counter + 1;
data = 4;
end
end
else if (digit == 2)
begin
if (counter == 400_000)
begin
digit = 3;
end
else
begin
counter = counter + 1;
data = 3;
end
end
else if (digit == 3)
begin
if (counter == 600_000)
begin
digit = 4;
end
else
begin
counter = counter + 1;
data = 2;
end
end
else if (digit == 4)
begin
if (counter == 800_000)
begin
digit = 1;
counter = 0;
end
else
begin
counter = counter + 1;
data = 1;
end
end
end
always # (*)
begin
case (data)
6'd0: cathodedata = 8'b00000011; //0
6'd1: cathodedata = 8'b10011111; //1
6'd2: cathodedata = 8'b00100101; //2
6'd3: cathodedata = 8'b00001101; //3
6'd4: cathodedata = 8'b10011001; //4
6'd5: cathodedata = 8'b01001001; //5
6'd6: cathodedata = 8'b01000001; //6
6'd7: cathodedata = 8'b00011111; //7
6'd8: cathodedata = 8'b00000001; //8
6'd9: cathodedata = 8'b00001001; //9
6'd10: cathodedata = 8'b00010001; //A
6'd11: cathodedata = 8'b11000001; //B
6'd12: cathodedata = 8'b01100011; //C
6'd13: cathodedata = 8'b10000101; //D
6'd14: cathodedata = 8'b00100001; //E
6'd15: cathodedata = 8'b01110001; //F
default: cathodedata = 8'b11111111; //default all off
endcase
if (setdp == 1) //decimal point
cathodedata = cathodedata & 8'hFE;
case(digit)
0: anodedata = 4'b1111; //all OFF
4: anodedata = 4'b1110; //AN0
3: anodedata = 4'b1101; //AN1
2: anodedata = 4'b1011; //AN2
1: anodedata = 4'b0111; //AN3
default:
anodedata = 4'b1111; //all OFF
endcase
end
endmodule
Here's a modified version of one of my pet projects. It should do exactly as you wanted: display 4 3 2 1 on the 4dig7seg display. I tested it on an Amani GTX CPLD, and it should transfer cleanly to your board.
I like separating projects into separate modules to keep organized. The top level module takes the on board clock as an input and outputs 14 signals to a four-digit-seven-segment serial display. Make sure the pins are correctly assigned.
module SevenSeg(clk, odig, onum, col, ap);
input clk; // 50 MHz oscillator
output [3:0] odig; // selected digit output
output [7:0] onum; // selected display output
output col = 1; // turns the colon off
output ap = 1; // turns the apostrophe off
wire clock; // divided oscillator to slow the display output
parameter a = 8'b11111110; // low means on, high means off
parameter b = 8'b11111101; // these are just parameters
parameter c = 8'b11111011; // defining each of the
parameter d = 8'b11110111; // seven segments
parameter e = 8'b11101111; // making life easier
parameter f = 8'b11011111;
parameter g = 8'b10111111;
parameter dp = 8'b01111111;
parameter off = 8'b11111111;
parameter one = b & c; // parameters for outputs
parameter two = a & b & d & e & g;
parameter three = a & b & c & d & g;
parameter four = b & c & f & g;
wire [7:0] port1 = one; // This is set up so these can change dynamically...
wire [7:0] port2 = two; // ... if so desired.
wire [7:0] port3 = three;
wire [7:0] port4 = four;
slowclk m1(clk, clock); // divides clk by 500, for 50 MHz in, 100 kHz out
digitize m2(clock, port1, port2, port3, port4, odig, onum); // rotates the digit outputs
endmodule
Next I have a simple clock divider. The case count = 500 can be modified to divide your clock to whatever frequency you like. The output should look fine in the range of about 120 Hz to about 2 MHz.
module slowclk(clk, clock);
input clk;
output reg clock;
integer count;
always #(posedge clk)
case(count)
500: begin clock <= clock + 1; count <= 0; end // Change 500 to any divisor you like
default: count <= count + 1;
endcase
endmodule
Then we have to rotate the digits. Note if you change the anodes and cathodes at the "same" time, there will be a small leakage current into the neighboring segments causing a "ghost" effect.
module digitize(clock, num1, num2, num3, num4, odig, onum);
input wire clock;
input [7:0] num1; // rightmost digit
input [7:0] num2;
input [7:0] num3;
input [7:0] num4; // leftmost digit
output reg [3:0] odig;
output reg [7:0] onum;
parameter [7:0] off = 8'b11111111;
reg [3:0] dstate;
always #(posedge clock)
case(dstate)
0:begin odig <= 4'b0001; dstate <= 1; end
1:begin onum <= num1; dstate <= 2; end
2:begin onum <= off; dstate <= 3; end // off states prevent 'ghosting'
3:begin odig <= 4'b0010; dstate <= 4; end // when changing output digit
4:begin onum <= num2; dstate <= 5; end
5:begin onum <= off; dstate <= 6; end
6:begin odig <= 4'b0100; dstate <= 7; end
7:begin onum <= num3; dstate <= 8; end
8:begin onum <= off; dstate <= 9; end
9:begin odig <= 4'b1000; dstate <= 10; end
10:begin onum <= num4; dstate <= 11; end
11:begin onum <= off; dstate <= 0; end
default: dstate <= 0;
endcase
endmodule
I too am using a basys2 and looking for a 7-seg driver. Nathan G's code did not work for me (using system verilog perhaps?), but I found this article: http://simplefpga.blogspot.co.uk/2012/12/scrolling-or-moving-text-using-7.html?showComment=1362783256904#c5783969326158067433 and I cannibalized it to my own ends.The modified code is below. It should take (although I haven't checked the decoding fully yet) four hex values and display them on the 7-seg. In my example my board now says 'FAAF' (because getting this working was faf)
ucf file taken from digilent site:
# Pin assignment for DispCtl
# Connected to Basys2 onBoard 7seg display
NET "seg<0>" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seg<1>" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seg<2>" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seg<3>" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seg<4>" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seg<5>" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seg<6>" LOC = "M12"; # Bank = 1, Signal name = CG
NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP
NET "an<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
NET "an<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "an<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "an<0>" LOC = "F12"; # Bank = 1, Signal name = AN0
Top level module has this:
module top_level(
//clock input
input CLK,
output [7:0] seg,
output dp,
output [3:0] an
);
scrolling_name scrolling_name(
.clock(CLK),
.reset(RESET),
.a(seg[0]),
.b(seg[1]),
.c(seg[2]),
.d(seg[3]),
.e(seg[4]),
.f(seg[5]),
.g(seg[6]),
.dp(dp),
.an(an),
//.XPosition(XPosition),
//.YPosition(YPosition)
.XPosition(8'hFA),
.YPosition(8'hAF)
);
endmodule
and the file I took from the guy in the link and have edited is:
`timescale 1ns / 1ps
module scrolling_name(
input clock,
input reset,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output dp,
output [3:0] an,
input [7:0] XPosition,
input [7:0] YPosition
);
reg [28:0] ticker; //to hold a count of 50M
wire click;
reg [3:0] fourth, third, second, first; // registers to hold the LED values
always # (posedge clock or posedge reset) //always block for the ticker
begin
if(reset)
ticker <= 0;
else if(ticker == 50000000) //reset after 1 second
ticker <= 0;
else
ticker <= ticker + 1;
end
reg [3:0] clickcount; //register to hold the count upto 9. That is why a 4 bit register is used. 3 bit would not have been enough.
assign click = ((ticker == 50000000)?1'b1:1'b0); //click every second
always # (posedge click or posedge reset)
begin
if(reset)
clickcount <= 0;
else if(clickcount == 8)
clickcount <= 0;
else
clickcount <= clickcount + 1;
end
always#(posedge clock)
begin
fourth = XPosition[7:4];
third = XPosition[3:0];
second = YPosition[7:4];
first = YPosition[3:0];
end
//see my other post on explanation of LED multiplexing.
localparam N = 18;
reg [N-1:0]count;
always # (posedge clock or posedge reset)
begin
if (reset)
count <= 0;
else
count <= count + 1;
end
reg [6:0]sseg;
reg [3:0]an_temp;
always # (*)
begin
case(count[N-1:N-2])
2'b00 :
begin
sseg = first;
an_temp = 4'b1110;
end
2'b01:
begin
sseg = second;
an_temp = 4'b1101;
end
2'b10:
begin
sseg = third;
an_temp = 4'b1011;
end
2'b11:
begin
sseg = fourth;
an_temp = 4'b0111;
end
endcase
end
assign an = an_temp;
reg [6:0] sseg_temp;
always # (*)
begin
case(sseg)
0 : sseg_temp = 7'b1000000; //to display 0
1 : sseg_temp = 7'b1001111; //to display 1
2 : sseg_temp = 7'b0100100; //to display 2
3 : sseg_temp = 7'b0110000; //to display 3
4 : sseg_temp = 7'b0011001; //to display 4
5 : sseg_temp = 7'b0010010; //to display 5
6 : sseg_temp = 7'b0000011; //to display 6
7 : sseg_temp = 7'b1111000; //to display 7
8 : sseg_temp = 7'b0000000; //to display 8
9 : sseg_temp = 7'b0011000; //to display 9
10 : sseg_temp = 7'b0001000; //to display A
11 : sseg_temp = 7'b0000011; //to display B
12 : sseg_temp = 7'b1000110; //to display C
13 : sseg_temp = 7'b0100001; //to display D
14 : sseg_temp = 7'b0000110; //to display E
15 : sseg_temp = 7'b0001110; //to display F
default : sseg_temp = 7'b1111111; //blank
endcase
end
assign {g, f, e, d, c, b, a} = sseg_temp;
assign dp = 1'b1;
endmodule
Please excuse the horrible formatting/indenting - there is a combination of his, mine, and adding four spaces to get stack overflow to recognize it as code. I don't have time to make things pretty unfortunately. I can bundle all this together and put it on dropbox if you would like.
Nathan
Towards the end you have :
always #(*) begin
...
if (setdp == 1) //decimal point
cathodedata = cathodedata & 8'hFE;
always #* implies a combinatorial block, that is no flip-flop to break up loops etc. Your simulator may not have caught this but I would expect it to have real problems in synthesis.
Basically you have cathodedata driving itself.
I would replace this with something like:
always #(*) begin
...
if (setdp == 1) //decimal point
cathodedata_mask = cathodedata & 8'hFE;
else
cathodedata_mask = cathodedata;

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