I am trying to do a VGA output using verilog but I can't seem to figure out why r_hcount stays X. The simulation waveforms show that r_vcount is being reset to 0 properly but for some reason r_hcount never gets reset to 0. I can't figure out why...
Verilog code:
module m_VGA640x480(
input wire iw_clock,
input wire iw_pix_stb,
input wire iw_rst,
output wire ow_hs,
output wire ow_vs,
output wire ow_blanking,
output wire ow_active,
output wire ow_screenend,
output wire ow_animate,
output wire [9:0] ow_x,
output wire [9:0] ow_y
);
localparam HS_STA = 16;
localparam HS_END = 16 + 96;
localparam HA_STA = 16 + 96 + 48;
localparam VS_STA = 480 + 11;
localparam VS_END = 400 + 11 + 2;
localparam VA_END = 480;
localparam LINE = 800;
localparam SCREEN = 524;
reg [9:0] r_hcount;
reg [9:0] r_vcount;
assign ow_hs = ~((r_hcount >= HS_STA) & (r_hcount < HS_END));
assign ow_vs = ~((r_vcount >= VS_STA) & (r_vcount < VS_END));
assign ow_x = (r_hcount < HA_STA) ? 0 : (r_hcount - HA_STA);
assign ow_y = (r_vcount >= VA_END) ? (VA_END - 1) : (r_vcount);
assign ow_blanking = ((r_hcount < HA_STA) | (r_vcount > VA_END - 1));
assign ow_active = ~((r_hcount < HA_STA) | (r_vcount > VA_END - 1));
assign ow_screenend = ((r_vcount == SCREEN - 1) & (r_hcount == LINE));
assign ow_animate = ((r_vcount ==VA_END - 1) & (r_hcount == LINE));
always #(posedge iw_clock)
begin
if (iw_rst)
begin
r_hcount <= 0;
r_vcount <= 0;
end
if (iw_pix_stb)
begin
if (r_hcount == LINE)
begin
r_hcount <= 0;
r_vcount <= r_vcount + 1;
end
else
r_hcount <= r_hcount + 1;
if (r_vcount == SCREEN)
r_vcount <= 0;
end
end
endmodule
Here is the result of the simulation. r_hcount is bugged... The code is supposed to set both counters to 0 when reset is 1 but for some reason it's not getting reset to 0. Please help.
Wavefrorm
From your work, I notice one point may cause the issue
always #(posedge iw_clock)
begin
if (iw_rst)
//you define r_hcount <= 0 here
.....
if (iw_pix_stb) //<== another condition
// r_hcount <= 0 is also defined here
So if posedge clock happened, r_hcount may be bugged here.
I suggest it should be done like this
else if (iw_pix_stb) <=== else if here
Good luck.
After tinkering a bit more with the code, I found out that it was because r_hcount <= 0 was getting overridden by r_hcount <= r_hcount + 1 which will set r_hcount to X. This was caused because the two clock inputs were both the same frequency.
I should be more careful in the future...
Related
I am facing an interesting issue in SystemVerilog where the comparison with a register isn't working.
module VGA_Colours
(
input wire clk, reset,
// input wire [3:0] swred, swgreen,
// input wire [1:0] swblue,
output wire hsync, vsync,
output wire [3:0] r, g, b
);
// constant declarations for VGA sync parameters
localparam H_DISPLAY = 640; // horizontal display area
localparam H_L_BORDER = 48; // horizontal left border
localparam H_R_BORDER = 16; // horizontal right border
localparam H_RETRACE = 96; // horizontal retrace
localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
localparam V_DISPLAY = 480; // vertical display area
localparam V_T_BORDER = 10; // vertical top border
localparam V_B_BORDER = 33; // vertical bottom border
localparam V_RETRACE = 2; // vertical retrace
localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
wire video_on, p_tick;
reg [9:0] ii;
reg j;
reg [3:0] red_reg, green_reg, blue_reg;
reg [11:0] rbg;
// mod-2 counter to generate 25 MHz pixel tick
reg pixel_reg = 0;
wire pixel_next;
wire pixel_tick;
always #(posedge clk)
pixel_reg <= pixel_next;
assign pixel_next = ~pixel_reg; // next state is complement of current
assign pixel_tick = (pixel_reg == 0); // assert tick half of the time
// registers to keep track of current pixel location
reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
// register to keep track of vsync and hsync signal states
reg vsync_reg, hsync_reg;
wire vsync_next, hsync_next;
// infer registers
always #(posedge clk)
if(~reset)
begin
v_count_reg <= 0;
h_count_reg <= 0;
vsync_reg <= 0;
hsync_reg <= 0;
end
else
begin
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
end
// next-state logic of horizontal vertical sync counters
always #*
begin
h_count_next = pixel_tick ?
h_count_reg == H_MAX ? 0 : h_count_reg + 1
: h_count_reg;
v_count_next = pixel_tick && h_count_reg == H_MAX ?
(v_count_reg == V_MAX ? 0 : v_count_reg + 1)
: v_count_reg;
end
// hsync and vsync are active low signals
// hsync signal asserted during horizontal retrace
assign hsync_next = h_count_reg >= START_H_RETRACE
&& h_count_reg <= END_H_RETRACE;
// vsync signal asserted during vertical retrace
assign vsync_next = v_count_reg >= START_V_RETRACE
&& v_count_reg <= END_V_RETRACE;
// video only on when pixels are in both horizontal and vertical display region
assign video_on = (h_count_reg < H_DISPLAY)
&& (v_count_reg < V_DISPLAY);
// output signals
assign hsync = hsync_reg;
assign vsync = vsync_reg;
assign p_tick = pixel_tick;
always #(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
ii <= ii + 9'b001010000;
rbg <= rbg + 12'b000010000000;
end
end
end
// output
assign r = (video_on) ? rbg[11:8] : 4'b0;
assign g = (video_on) ? rbg[7:4] : 4'b0;
assign b = (video_on) ? rbg[3:0] : 4'b0;
endmodule
In the above code h_count_reg is 0 works fine. If I change 0 to any different number, it will work as expected. However, if I replace that number with a variable (which is "ii", declared on top of my module as reg[9:0] ii), the code seems to ignore it, which is weird. Replacing the ii variable with any number will work. Why?
TestBench file:
module VGA_Colours_tb ();
logic clk;
reg reset;
wire hsync, vsync;
wire [3:0] r, g, b;
VGA_Colours scr0 (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.r (r),
.b (b),
.g (g)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
always #(posedge clk) begin
#20
reset <= 1'b0;
#20
reset <= 1'b1;
#100000
$finish;
end
endmodule
Simulation wave:
As you can see from the code, when h_count_reg is == to ii, increment the rbg and the value of ii. However, based on the simulation waves, it is not doing that as if the value of h_count_reg is not equal to ii while it actually is.
You have a logic error in the VGA_Colours module.
Here is your code with more consistent indentation:
always #(posedge p_tick) begin
if (~reset) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else begin
if (h_count_reg == 0) begin
rbg <= 12'b000000000000;
ii <= 9'b0;
end else if (h_count_reg == ii) begin
rbg <= rbg + 12'b000010000000;
ii <= ii + 9'b001010000;
end
end
end
When I run your simulation, I observe ii is always 0 after the initial reset.
The code has 3 if statements. The 1st if statement is true at the beginning of the simulation, when reset=0. This sets ii to 0.
After reset, I see h_count_reg=0 4 times. This means the 2nd if statement is true 4 times. This keeps ii = 0.
The 3rd if statement is evaluated only when h_count_reg is not 0. It should be clear now that the 3rd if statement can never be true. This means that ii will not be incremented and it will remain at 0. For example, when h_count_reg=1, then (h_count_reg == ii) is false because ii is always 0.
I'm making a simple project with leds blinking every second. Led 1 and 3 blink alternating to led 2 and 4. I've written the following Verilog code:
module leds_blinking(input i_Clk,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4);
parameter c_CYCLESINSECOND = 50_000_000;
reg r_LED_1 = 1;
reg r_LED_2 = 0;
reg r_LED_3 = 1;
reg r_LED_4 = 0;
reg [32:0] r_Count = 0;
always #(posedge i_Clk)
begin
if (r_Count < c_CYCLESINSECOND)
r_Count <= r_Count + 1;
else if (r_Count == c_CYCLESINSECOND)
begin
r_LED_1 <= ~r_LED_1;
r_LED_2 <= ~r_LED_2;
r_LED_3 <= ~r_LED_3;
r_LED_4 <= ~r_LED_4;
r_Count <= 0;
end
else
r_Count <= 0;
end
assign o_LED_1 = r_LED_1;
assign o_LED_2 = r_LED_2;
assign o_LED_3 = r_LED_3;
assign o_LED_4 = r_LED_4;
endmodule
All LEDs are active at the same time, though I instantiated 1,3 other than 2,4.
I’m assuming you are synthesizing and not running simulation on the RTL first. Synthesizer that target for ASIC typically ignore default values and initial blocks. Synthesizer that target for FPGA often do. Not knowing which synthesizer you are using it is hard to guess your root causes issue.
However, you can simplify your code and solve your problem by using one registers instead of four. Notice how the o_LED_# are driven.
always #(posedge i_Clk)
begin
if (r_Count < c_CYCLESINSECOND)
r_Count <= r_Count + 1;
else
begin
r_LED <= ~r_LED;
r_Count <= 0;
end
end
assign o_LED_1 = r_LED;
assign o_LED_2 = ~r_LED;
assign o_LED_3 = r_LED;
assign o_LED_4 = ~r_LED;
I'm very new to verilog and I am stuck on a project I am writing to get better at it. I have a button and an LED on my board, and I want the button to increment a counter which makes the led flash faster. This seems to work in theory but I cannot get it to work in practice. The switch won't make the led flash faster, it seems to do some strange things.
My current code, please inform me of any issues with what I'm doing even if it does not cause my issue here as I am trying to learn the langauge and constructs.
`timescale 1ns / 1ps
module LedFlash(CLK100MHZ, led0, sw0, btn0);
input CLK100MHZ;
output reg led0;
input sw0;
input btn0;
reg [25:0] clockTick = 0;
reg [1:0]currentlyLighting = 0;
reg [3:0] speedFactor = 0;
reg [1:0]oldButton = 0;
reg [1:0]buttonValue = 0;
always #(posedge CLK100MHZ)
begin
led0 <= 0;
buttonValue <= 0;
if(oldButton != btn0 && btn0 == 1)
buttonValue <= 1;
oldButton <= btn0;
if(clockTick == 0)
currentlyLighting <= !currentlyLighting;
if(currentlyLighting)
led0 <= 1;
if(buttonValue) begin
speedFactor <= speedFactor + 1;
end
clockTick <= clockTick + speedFactor;
end
endmodule
Here is a gif of a couple presses of the button. Only the times when speedfactor increments is when I actually press the button.
I would provide more presses, but it just gets more strange from there, clearly I am doing something wrong.
After that initial press of the button, it strays away from what I expect. Sometimes it turns off, sometimes stays solid, slows down, speeds up.....
**Also, if I replace this line :
clockTick <= clockTick + speedFactor;
with
clockTick <= clockTick + 10;
for example, it will flash fast like I would expect it to. I'm guessing I am doing something wrong with the bit addition, although the probe seems to tell me otherwise.
**
Fixed code :
`timescale 1ns / 1ps
module LedFlash(CLK100MHZ, led0, sw0, btn0);
input CLK100MHZ;
output reg led0;
input sw0;
input btn0;
reg [25:0] clockTick = 0;
reg currentlyLighting = 0;
reg [3:0] speedFactor = 0;
reg oldButton = 0;
reg buttonValue = 0;
always #(posedge CLK100MHZ)
begin
led0 <= 0;
buttonValue <= 0;
if(oldButton != btn0 && btn0 == 1)
buttonValue <= 1;
oldButton <= btn0;
currentlyLighting <= clockTick[25];
if(currentlyLighting && sw0)
led0 <= 1;
if(buttonValue) begin
speedFactor <= speedFactor + 1;
end
clockTick <= clockTick + speedFactor;
end
endmodule
The design doesn't ensure that clockTick hits 0 while starting a new round, so speedFactor actually cannot control the toggling frequency of currentlyLighting.
For example, if clockTick is 26'h3FFFFFF and speedFactor is 4'd3, the next value of clockTick will be 26'h0000002 and currentlyLighting will not toggle for that round.
An easy solution could be using the MSB of clockTick as currentlyLighting.
currentlyLighting <= clockTick[25];
In addition; buttonValue, oldButton and currentlyLighting should be single-bit signals, but they are 2-bit in your code. The correct declarations are as follows.
reg currentlyLighting = 0;
reg oldButton = 0;
reg buttonValue = 0;
This is code for ALU that does addition and multiplication only. An addition is handled in same clock cycle but the multiplication result has to be delayed by 3 clock cycles.
module my_addmul(
//control signals
input i_clk,
input i_rst,
input i_en,
//add=01, mul=10
input [1:0] i_op,
//input and output registers
input [31:0] i_A,
input [31:0] i_B,
output [31:0] o_D,
//to signal if output is valid
output o_done
);
//registers to save output
reg [31:0] r_D;
reg [63:0] r_mul;//(*keep="true"*)
reg r_mul_done;
reg r_mul_done2;
reg r_done;
//updating outputs
assign o_D = r_D;
assign o_done = r_done;
always # (posedge i_clk)
begin
r_done <= 0;
r_mul_done <= 0;
if (i_rst) begin
r_D <= 0;
r_mul <= 0;
r_mul_done <= 0;
r_mul_done2 <= 0;
end else if (i_clk == 1) begin
if (i_en == 1) begin
//addition - assignment directly to OP registers
if (i_op == 01) begin
r_done <= 1;
r_D <= i_A + i_B;
//multiplication - indirect assignment to OP registers
end else if (i_op == 2'b10) begin
r_mul <= i_A * i_B;
r_mul_done <= 1;
end
end
//1-clock cycle delay
r_mul_done2 <= (r_mul_done == 1) ? 1 : 0;
//updating outputs in the 3rd cycle
if (r_mul_done2 == 1) begin
r_D <= r_mul[31:0];
r_done <= 1;
end
end
end
endmodule
The problem is that if the keep attribute is not used, the r_mul register that stores the multiplication output until 3rd clock cycle is optimised out. I read on the problem and realised that Vivado is thinking like this: "If the multiplication happens every clock cycle, the r_mul is over-written before it is sent to output. Therefore, it is a register being written but not read, Lets remove it!" Since I insert the 3 clock cycle wait in test bench, the simulation result is always accurate. I want to know what is the "Proper" way of doing this so I don't have to use the keep attribute. It is an ok solution but I think useful techniques should be learned so hacks don't have to be used. Any ideas or discussion welcome.
If I want to delay a signal, I'd probably insert flops for that. You can probably flop your mul_output like the way you do for the mul_done signal. Also, it is better to have different always blocks for doing the same. You can check the code below but it might be buggy since I haven't simulated/synthesized it -
module my_addmul(
//control signals
input i_clk,
input i_rst,
input i_en,
//add=01, mul=10
input [1:0] i_op,
//input and output registers
input [31:0] i_A,
input [31:0] i_B,
output [31:0] o_D,
//to signal if output is valid
output o_done
);
//registers to save output
reg [31:0] r_D;
reg [63:0] r_mul;//(*keep="true"*)
reg r_mul_1;
reg r_mul_2;
reg r_mul_done;
reg r_mul_done2;
reg r_done;
//updating outputs
assign o_D = r_D;
assign o_done = r_done;
always # (posedge i_clk)
begin
r_done <= 0;
r_mul_done <= 0;
if (i_rst) begin
r_D <= 0;
r_mul <= 0;
r_mul_done <= 0;
r_mul_done2 <= 0;
end else if (i_clk == 1) begin
if (i_en == 1) begin
//addition - assignment directly to OP registers
if (i_op == 01) begin
r_done <= 1;
r_D <= i_A + i_B;
//multiplication - indirect assignment to OP registers
end else if (i_op == 2'b10) begin
r_mul <= i_A * i_B;
r_mul_done <= 1;
end
end
end
end
always # (posedge i_clk)
begin
if (i_rst)
begin
r_mul_1 <= 0;
r_mul_done2 <= 0;
end
else
begin
r_mul_1 <= r_mul;
r_mul_done2 <= r_mul_done;
end
end
always # (posedge i_clk)
begin
if (i_rst)
begin
r_D <= 0;
r_done <= 0;
end
else
begin
r_D <= r_mul_1;
r_done <= r_mul_done2;
end
end
endmodule
I have created this code for vga controller and the simulation is proper too. The problem is the monitor is blank when code runs, also in the waveform generation the two output's hsync and vsync are displayed '0'. I have no idea where the logic goes wrong. Please help.
Code :
module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);
// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 56; // front porch (right border)
localparam HB = 64; //right porch (left border)
localparam HR = 120; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 37; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 6; // vertical retrace
//horizontal and vertical counter
reg [9:0] h_count = 0;
reg [9:0] v_count = 0;
wire [9:0] h_end,v_end;
assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;
always #(*) begin
if(clk)
if(h_end)
h_count = 0;
else
h_count = h_count+1;
else
h_count = h_count;
end
always #(posedge clk) begin
if(h_end)
if(v_count<v_end)
v_count = v_count+1;
else
v_count = 0;
else
v_count = v_count;
end
assign hsynch = ((h_count >= HD+HF-1) && (h_count <= HD+HF+HR+HB-1));
assign vsynch = ((v_count >= VD+VF-1) && (v_count <= VD+VF+VR+VB-1));
assign video_on = ((h_count < HD) && (v_count < VD));
wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 10'b0;
assign pixel_y = (video_on)? v_count : 10'b0;
reg [7:0] coloroutput;
always #(clk)
if(~video_on)
coloroutput <= 0;
else begin
if( pixel_x<150 && pixel_y<160)
coloroutput[7:5] <= 3'b111;
else if(pixel_x<250 && pixel_y<320)
coloroutput[4:2] <= 3'b111;
else
coloroutput[1:0] <= 2'b11;
end
assign red = (video_on) ? coloroutput[7:5] : 3'b000;
assign green = (video_on) ? coloroutput[4:2] : 3'b000;
assign blue = (video_on) ? coloroutput[1:0] : 3'b000;
endmodule
You should definitely try simulating this. I'm pretty sure you'll find that your code doesn't work in simulation. Always check your code in a simulation environment before trying to program your FPGA! You have this line:
always #(*) begin
if(clk)
if(h_end)
h_count = 0;
h_end is a static value, you need to be comparing it to something. Maybe:
if (h_count == h_end)
something like that. Additionally, this always block should tell the tools to look for a rising edge on your clock signal. E.g.
always #(posedge clk) begin
if (h_count == h_end)