"Illegal reference to memory" in Verilog switch case - switch-statement

Question

I am trying to write a Finite State Machine for an assignment. However, I don't understand what is wrong with my module code. I get the error:
ERROR VCP5221 "Illegal reference to memory: st." "design.sv" 77 5
when I try to synthesize. I think I've either misunderstood how switch-case is used in Verilog or I've attempted to make an illegal assignment inside the switch-case but I don't know how to find it.
//Code here
module MooreFSM(
input clk,
input in,
output out
);
reg state[2:0];
reg sel[2:0];
reg o;
assign out = o;
initial begin
state <= 3'b000;
o <= 1'b0;
end
always#(negedge clk) begin
state <= sel;
end
always#(posedge clk) begin
case(state)
3'b000: begin
if(in == 1'b0) begin
sel <= 3'b010;
o <= 1'b0;
end
else if(in == 1'b1) begin
sel <= 3'b001;
o <= 1'b0;
end
end
3'b001: begin
if(in == 1'b0) begin
sel <= 3'b000;
o <= 1'b0;
end
else if(in == 1'b1) begin
state <= 3'b011;
o <= 1'b0;
end
end
3'b010: begin
if(in == 1'b0) begin
sel <= 3'b100;
o <= 1'b0;
end
else if(in == 1'b1) begin
sel <= 3'b000;
o <= 1'b0;
end
end
3'b011: begin
if(in == 1'b0) begin
sel <= 3'b000;
o <= 1'b1;
end
else if(in == 1'b1) begin
sel <= 3'b011;
o <= 1'b1;
end
end
3'b100: begin
if(in == 1'b0) begin
sel <= 3'b100;
o <= 1'b1;
end
else if(in == 1'b1) begin
sel <= 3'b000;
o <= 1'b1;
end
end
default: begin
sel <= 3'b000;
o <= 1'b0;
end
endcase
end
endmodule
Please help me identify the problem, or if I need to use a different method to synthesize a mux.

Answer 1

I think when you put
else if(in == 1'b1) begin
state <= 3'b011;
o <= 1'b0;
end
you might have meant to write
else if(in == 1'b1) begin
sel <= 3'b011;
o <= 1'b0;
end
By putting state as something being assigned in just one case of this switch statement, you're implicitly asking for it to be latched back to in every other case, which conflicts with you explicitly making it a flop above.