This is my code. But when I compile this, I got error messages.
What's wrong with my code?
// seg7dec.v
module seg7dec (
input [3:0] val,
output reg [6:0] seg // from MSB A, B, C, D, E, F, G
);
always #(*)
begin
case (val[3:0])
4'h0: seg[6:0] = 7'b111_1110;
4'h1: seg[6:0] = 7'b011_0000;
4'h2: seg[6;0] = 7'b110_1101;
4'h3: seg[6;0] = 7'b111_1001;
4'h4: seg[6;0] = 7'b011_0011;
4'h5: seg[6;0] = 7'b101_1011;
4'h6: seg[6;0] = 7'b101_1111;
4'h7: seg[6;0] = 7'b111_0000;
4'h8: seg[6;0] = 7'b111_1111;
4'h9: seg[6;0] = 7'b111_1011;
4'ha: seg[6;0] = 7'b111_1101;
4'hb: seg[6;0] = 7'b001_1111;
4'hc: seg[6;0] = 7'b100_1110;
4'hd: seg[6;0] = 7'b100_1111;
4'hg: seg[6;0] = 7'b111_1011;
default: seg[6:0] = 7'b100_0111 ; // 4'hF
endcase
end
endmodule
These are the error messages:
;'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(14): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(15): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(16): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(17): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(18): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(19): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(20): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(21): near ";": syntax error, unexpected ';'.
** Error: (vlog-13069) C:/Intel/seg7dec.v(22): near ";": syntax error, unexpected ';'.
** Error: (vlog-13057) C:/Intel/seg7dec.v(23): Expecting numeric digits.
** Error: (vlog-13069) C:/Intel/seg7dec.v(23): near "g": syntax error, unexpected IDENTIFIER, expecting ':'.
From the line
4'h2: seg[6;0] = 7'b110_1101;
You have added ; instead of : between 6 and 0.
When using partial select, the format should be [MSB:LSB].
So you need to change seg[6;0] to seg[6:0].
Or, since seg is declared as 7-bit wide, it's not necessary to add [6:0] to seg.
The last 4'hg should be 4'he.
Related
So, I created my first system Verilog testbench by modifying the tutorial from https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-01/ ( In this tutorial a memory block is tested, I modified it for a simple AND gate).
There are seven files excluding the DUT file,
environment.sv
interface.sv
transactions.sv
generator.sv
testbench.sv ( topLevel testbench)
driver.sv
test.sv
I used Intel modelsim to compile these files.
While compiling, I got these errors in driver.sv and generator.sv
** Error: (vlog-13069) D:/Altera/Projects/AndGate/testbench/driver.sv(28): near ";": syntax error, unexpected ';', expecting '('.
** Error: (vlog-13069) D:/Altera/Projects/AndGate/testbench/generator.sv(4): near "trans": syntax error, unexpected IDENTIFIER, expecting ';' or ','.
Below are the corresponding files,
driver.sv
`define DRIV_IF mem_vif.DRIVER.driver_cb
class driver;
int num_trans;
virtual mem_intf mem_vif;
mailbox gen2driv;
function new(virtual mem_intf mem_vif, mailbox gen2driv);
this.mem_vif = mem_vif;
this.gen2driv = gen2driv;
endfunction
task reset();
wait(mem_vif.reset);
$display("--------- [DRIVER] Reset Started ---------");
`DRIV_IF.A <= 0;
`DRIV_IF.B <= 0;
`DRIV_IF.C <= 0;
wait(!mem_vif.reset);
$display("--------- [DRIVER] Reset Ended ---------");
endtask
task drive();
transaction trans;
gen2driv.get(trans);
$display("Num transactions : %0d", num_trans);
#(posedge mem_vif.DRIVER.clk);
`DRIV_IF.A <= trans.A;
`DRIV_IF.B <= trans.B;
trans.C = `DRIV_IF.C;
$display("\tA = %0h \tB = %0h \tC = %0h", trans.A, trans.B, `DRIV_IF.C);
num_trans++;
endtask
endclass
generator.sv
class generator;
var rand transaction trans;
mailbox gen2driv;
int repeat_count;
event ended;
function new(mailbox gen2driv, event ended);
this.gen2driv = gen2driv;
this.ended = ended;
endfunction
task main();
repeat(repeat_count) begin
trans = new();
if(!trans.randomize())$fatal("Random Generation failed");
gen2driv.put(trans);
end
-> ended;
endtask
endclass
Please, help me with this...
For future reference, it would really help to point to the line 28 and 4 in the respective files where the error is occurring as well as give the command line used to compile the code. But since I've seen this exact error before, I know it is because you put all of these files separately on your command line and not compiled together as a package.
Modelsim/Questa compiles every SystemVerilog file on the command line as a separate compilation unit. Identifiers declared in one compilation unit cannot be seen by other compilation units. When the generator and driver classes get compiled, it has no idea what transaction means and you get a syntax error. Modules and interfaces names exist in a separate namespace and the syntax where they are referenced allows them to used before their declarations have been compiled.
To remedy this, you could `include all you class files in testbench module, or the normal practice is putting them all in a package and importing the package. There is also a compilation mode where everything on the command line in one compilation unit, but that option is not scaleable as your designer get larger.
I also suggest reading these two posts I wrote:
https://blogs.sw.siemens.com/verificationhorizons/2010/07/13/package-import-versus-include/
https://blogs.sw.siemens.com/verificationhorizons/2009/05/07/programblocks/
I'm doing a Multiplex 4x1 in Verilog using EDAPlayground, but I still get testbench errors, and I don't know why.
Here is one error:
ERROR VCP2000 "Syntax error. Unexpected token: and[_AND]." "design.sv"
26 6
module mux4x1(
input x1, x2, x3, x4, s0, s1,
output f);
wire s0_inv, out_x1, out_x2;
wire s1_inv, out_x3, out_x4;
wire out_mux1, out_mux2;
wire out_mux3, out_mux4;
// mux2x1_1
not (s1_inv, s1);
and (out_x1, s1_inv, x1);
and (out_x2, s1, x2);
or (out_mux1, out_x1, out_x2);
// mux2x1_2
not (s1_inv, s1);
and (out_x3, s1_inv, x3);
and (out_x4, s1, x4);
or (out_mux2, out_x3, out_x4);
// mux4x1
not (s0_inv, s0)
and (out_mux3, s0_inv, out_mux1);
and (out_mux4, s0_inv, out_mux2);
or (f, out_mux3, out_mux4);
endmodule
Link: https://www.edaplayground.com/x/bkNc
When I try to compile just your design code, I get this error:
and (out_mux3, s0_inv, out_mux1);
|
xmvlog: *E,EXPSMC : expecting a semicolon (';') [7.1(IEEE)].
Often this type of error is caused by the line of code above the reported line:
not (s0_inv, s0)
Just add the semicolon:
not (s0_inv, s0);
EDAplayground offers several different simulators, and some provide more helpful error messages than others. You have it set for Aldec; switch to Cadence, for example, to see a different error message.
I downloaded the memory model for the DDR3 bank that I'd be testing in simulation using Modelsim (2019.2) from Micron's website (link).
I followed the instructions from the README file to compile it but I run into syntax errors! I don't think Micron would make bug-gy code public and available to developers.
Modelsim command:
vlog +define+sg25 C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v
ERRORS
# ** Error: (vlog-13069) C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(421): near ";": syntax error, unexpected ';', expecting '('.
# ** Error: C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(424): Illegal declaration after the statement near line '421'. Declarations must precede statements. Look for stray semicolons.
# ** Error: (vlog-13069) C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(433): near "integer": syntax error, unexpected integer, expecting IDENTIFIER or genvar.
# ** Error: C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(433): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?
initial
begin : file_io_open
reg [BA_BITS - 1 : 0] bank;
reg [ROW_BITS - 1 : 0] row;
reg [COL_BITS - 1 : 0] col;
reg [BA_BITS + ROW_BITS + COL_BITS - 1 : 0] addr;
reg [BL_MAX * DQ_BITS - 1 : 0] data;
string _char; //LINE 421
integer in, fio_status;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (integer i = 0; i < `BANKS; i = i + 1)
memfd[i] = open_bank_file(i);
I hope someone can suggest me how to proceed with it. I have contacted Micron but haven't heard from them yet (it has been a few days). I am stuck and any comments are appreciated!
Thank you,
Surabhi
The error is from the line which includes string, which is a SystemVerilog keyword.
You need to enable SystemVerilog syntax using the modelsim -sv option.
I am getting the following error when i try to assign the value to var.
unsigned long var= 0x7137449123ef65cdULL;
Is unsigned long long supported in vc++6?
Error:-
Error 1 error C2059: syntax error : 'bad suffix on number'
Solution
Based on the inputs from RogerRowland and Igor Tandetnik i resolved this issue.
Solution:
"unsigned __int64 var= 0x7137449123ef65cdi64;
Is it possible to get 21 errors for a 20 line program in Any language? Any platform. ? Sorry if this should not be asked. I m new to programming. My trainer asked me this question. Can someone help or explain? Thanks in advance.
C++:
trolo = lolo; //1 line
Errors:
error C2065: 'trolo' : undeclared identifier
error C2065: 'lolo' : undeclared identifier
C#:
al; cas; r; sb; ds; es; ew; qw; 2; 32; a; int a = 2.3;
1 line, exactly 21 errors.:D