I have two modules 'wired' together. One is a simple sequence detector and one is a counter.
Here are the two signatures of the methods:
module Detector1010 (input [3:0] co_in, input j, clk, rst, output w, output reg init, output reg en);
module counter (input clk, rst, en, init, output reg [3:0] co );
Essentially that output register 'co' in the counter is intended to be readable from the Dector1010 module (hence the co_in) variable. The reason for that is I want to be able to detect when the co reaches a certain value, to perform some sort of action.
Within 'Detector1010' there is always block which checks the value of 'co_in'
$display("sleep! %d", co_in);
if(co_in == 4'b1111) begin
//reached 16!
$display("reached 16!");
end
Here I am just waiting for the counter value to reach 16 and printing what it is each time the always block executes. (How often does that execute? It seems to run just constantly and not on a clock.. I guess the whole point is its always running?). However by display instead prints:
"sleep! x"
As if the actual value of that register does not get passed in. I was using a wire to connect the two modules, so I thought this sort of input is allowed:
wire [3:0] co;
wire init;
wire en;
assign co = 4'b0000;
Detector1010 det(co, j, clk, rst, w, init, en);
counter cnt(clk, rst, en, init, co);
as I figured the 'co' variable would just work as a databus between the detector and the counter modules. I guess I am misunderstanding how that variable works? Not really sure what I am doing wrong here!
I can post the whole code example. I was trying to just keep it concise.
You have contention on the co signal which results in x. Remove this line:
assign co = 4'b0000;
Your counter module drives the co output signal, but your testbench continually drives it to 0, at all times starting at time 0. co would normally be initialized inside the counter module.
Related
I'm confused about connection, I want to use ALU to call RippleCarry module, and I need to do branch without always block and Procedure Assignment.
I don't know what method is best. I see others have written in TestBench.v or ALU.v.
Here's my code.
ALU.v
module ALU( Signal, a, b, Output );
input [31:0] a, b;
input [5:0] Signal;
output [31:0] Output;
// write here ? or write into test bench?
// if Signal is 6'd35, do RippleCarry.
/*RippleCarry RC( .a(a), .b(b), .Sum(Output) ); */
endmodule
RippleCarray.v
module RippleCarry(
input [31:0] a, b,
input Cin,
output Cout,
output [31:0] Sum
);
In verilog, modules are not called, but instantiated. Unlike traditional programming, verilog is a hardware descriptive language; meaning it is code describing hardware, not specifying instructions to be run by a cpu as you do in typically programming languages. Hardware doesn't materialize and dematerialize when signals take on different values; the control signals simply define which of many different data paths is connected between input and output.
In your case, you wouldnt write something like this:
module ALU(...)
if (Signal == 6'd35) begin
RippleCarry RC(...);
end
endmodule
Since Signal is a control line that changes value as the hardware runs, this would imply the ripple carry adder exists when the Signal is 35 and disappears when it's not.
Instead, the adder should be instantiated, it exists in the design and it always there. The problem now is to direct it's output to the output of the ALU only when Signal is 35.
module ALU(input [5:0] Signal,
input [31:0] a, b,
output reg [31:0] Output); // Note, I made Output a reg so I can use always, it doesn't mean it's actually a register
wire [31:0] rcOutput;
// Instantiate the RC adder so it exists in the hardware
RippleCarry RC(.a(a), .b(b), .Sum(rcOutput));
// Direct the output of the RippleCarry adder to the output only when signal is 35, otherwise just leave it at 0.
// Use switch here to make it easy to add more operations later
always #(*) begin
Output = 32'd0; // default
case (Signal)
6'd35: Output = rcOutput; // rc add
endcase
end
endmodule
Edit: I see now you want to do it without using always or assign, which doesn't change the fundamental design but makes it more obscure and less scalable, which is why I'm leaving the above as a reference. In the case we only have one op code for signal, we can simply implement the logic that compares signal to 35 and masks output if not equal in gates:
// Replace the always block with the below, though it's certainly not as nice, it's a possible implementation of that always block in gates
wire [5:0] SignalN;
wire SignalIs35;
not g1[5:0](SignalN, Signal);
// 35 is 100011 in binary, so see if Signal is that value
and g2(SignalIs35, Signal[5], SignalN[4], SignalN[3], SignalN[2], Signal[1], Signal[0]);
and g3[31:0](Output, rcOutput, {32{SignalIs35}});
In the following code:
wire a;
reg b;
assign a = b;
ModuleName foo(a, other wire inputs, ... , wire outputs);
Assume that they are part of a top level module.
I wanted to run an always# block but make changes in the input of a module instantiated in this module.
always#(*) b = c^d; //Some Logic
The thing is, they are wires and cannot be on the LHS in an always# block. Can I make changes to band expect to see them in a i.e. the input of the Module foo.
Yes. Every time you change b, a will change too. That is what an assign statement does. Remember this is hardware. The statement
assign a = b;
means 'drive wire a with whatever value reg b has for all time'.
I'm was following a tutorial to blink a led in my fpga.
These are the codes presented :
1)
module LED (
input [17:0] SW,
output reg [17:0] LEDR
);
assign led = switch;
endmodule
2) --------
module LED (
input [17:0] SW,
output reg [17:0] LEDR
);
always #(*)
led = switch;
endmodule
3) ---------
module LED (
input CLOCK_50,
input [17:0] SW,
output reg [17:0] LEDR
);
always #(posedge CLOCK_50)
LEDR = SW;
endmodule
Your first example uses continuous assignment to set the value of led to the value of switch. It's like connecting led and switch directly with a wire. Whenever switch changes, led also changes.
Your second example does the same thing but uses an always block. always blocks have a sensitivity list, which contains signals that will trigger the block to run. In this case, it's *, meaning that it triggers any time any of the signals in the blocks change. I believe this is identical to your first example.
Your third example uses sequential logic to set LEDR to SW. In this case, the always block triggers only when the CLOCK_50 signal goes high from a non-high state. If CLOCK_50 never rises, LEDR is never set to any value.
By the way, I don't think your first or second examples are synthesizable. I think led and switch should be LEDR and SW.
These articles give a better description of the concepts in your examples:
Assignments : http://verilog.renerta.com/mobile/source/vrg00005.htm
Always Blocks: http://www.asic-world.com/verilog/verilog_one_day3.html
For our school project I am trying to use linear feedback shift register for pseudo-random number generation on hardware (seven segment). I have written the LFSR and seven segment module, however I have trouble connecting the two modules with each other. The project synthesizes but the HDL Diagram does not show any connection between LFSR and seven segment module. Below is the code.
//main module
module expo(input clock, reset,
output a,b,c,d,e,f,g
);
wire [3:0]connect, clk, a,b,c,d,e,f,g;
LFSR_4_bit lfsr(
.clock(clock),
.LFSR(connect)
);
seven_seg seven(
.in(connect),
.reset(reset),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g)
);
endmodule
//LFSR module
module LFSR_4_bit(
input clock,
output reg[3:0]LFSR = 15
);
wire feedback = LFSR[4];
always #(posedge clock)
begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1];
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3];
end
endmodule
//input and output for seven seg module
module sevenseg(
input reset,
input[3:0] in, //the 4 inputs for each display
output a, b, c, d, e, f, g, //the individual LED output for the seven segment along with the digital point
output [3:0] an // the 4 bit enable signal
);
Thanks for the help.
1) You instantiate seven_seg but the module is called module sevenseg This is a compile error.
2) Your LFSR has 4 bits 0 to 3, a fifth bit LFSR[4] is used, this is also a compile error.
Due to the compile errors I am not sure that your viewing the results of the current synthesis, as it should have failed. It is quite likely that you are viewing an old result before they were connected.
Other things I would change:
a) When you define wire [3:0]connect, clk, a,b,c,d,e,f,g; they are all 4 bits.
However as clock (not clk) and a,b,c,d,e,f,g are defined in your port list they are already declared. That line could just be wire [3:0]connect.
b) When initialising values for flip-flop and not using a reset it is better practise to use an initial begin : This is valid for FPGA's not for ASICs where you should use reset signals
initial begin
LFSR = 4'd15;
end
I'm trying to use two switches to select the frequency I want to blink the led's at. My verilog code is as follows:
`timescale 1ns / 1ps
module clk_divider(
input clk,
input rst,
input [1:0] sw,
output led
);
reg n;
always#(sw[0],sw[1])
n = (27 - sw);
wire [n-1:0] din;
wire [n-1:0] clkdiv;
dff dff_inst0 (
.clk(clk),
.rst(rst),
.D(din[0]),
.Q(clkdiv[0])
);
genvar i;
generate
for (i = 1; i < n; i=i+1)
begin : dff_gen_label
dff dff_inst (
.clk(clkdiv[i-1]),
.rst(rst),
.D(din[i]),
.Q(clkdiv[i])
);
end
endgenerate;
assign din = ~clkdiv;
assign led = clkdiv[n-1];
endmodule
When I check for syntax, it says that "n is not constant." How can I avoid this error? To me, it seems that it should work. Any help would be appreciated!!!
With respect to wire [n-1:0] din; and wire [n-1:0] clkdiv;, you cannot have the width of a bus dependent on the value of an input.
A bus width is defined at synthesis time, it is the number of wires that exist in the physical device. Wires cannot appear or disappear based on the state of a module input or register.
You need to define these wires as having a fixed width, not a dynamic width. Maybe in some cases not all the wires will be used, but you must still define the bus as the maximum width that you will ever need. Similarly in the generate loop, you cannot change the number of flip-flops that are instantiated based on the value of n. You must instantiate as many flip flops as you will ever need, and then enable/disable some as needed.
Also you will hit this separate issue later, but your register n is only a single bit, so it cannot store any number other than 0 or 1. Make the register larger if you intend to hold greater values.