Verilog not calculating wire values - verilog

Question

I'm attempting to visualize some code from here. However, the wire values I'm trying to view (all the reqs and acks in SIMSYS) are displaying as 'x'.
I don't know enough about any HDLs to know what is going wrong, so I'd appreciate an explanation of what's going on. If it makes any difference, I'm running it with iverilog 10.2 on Ubuntu 19.04.
Here's the code in question:
// A Muller C-element
module MCEL (q, a, b);
input a, b;
output q;
wire reset;
wire p1 = !(a & q);
wire q1 = !(b & q);
wire r1 = !(a & b);
assign #13 q = !(p1 & q1 & r1);
endmodule
//Micropipeline stage (David Sutherland style).
module MPHSL(req_l, ack_l, req_r, ack_r, din,dout);
input req_l; output ack_l;
output req_r; input ack_r;
MCEL left(ack_l, req_l, !req_r);
MCEL right(req_r, ack_l, !ack_r);
// Data handling stage
input [7:0] din;
output [7:0] dout;
reg [7:0] dout1;
always #(posedge req_l) dout1 <= din;
assign dout = dout1;
endmodule
// Simulation wrapper
module SIMSYS();
wire req_1, ack_1;
wire req_2, ack_2;
wire req_3, ack_3;
wire req_4, ack_4;
reg tn;
initial begin tn = 0; #350 tn = 1; # 20 tn = 0; end
wire [7:0] d1,d2,d3,d4;
MPHSL s1(tn | req_4, ack_4, req_1, ack_1, (tn)? 8'hx5A: d4+1, d1);
MPHSL s2(req_1, ack_1, req_2, ack_2, d1, d2);
MPHSL s3(req_2, ack_2, req_3, ack_3, d2, d3);
MPHSL s4(req_3, ack_3, req_4, ack_4, d3, d4);
endmodule

Answer 1

The issue is that there are no initial values and no logic that resets any variables to a valid state, so the code is forever propagating X values. The first thing you need to do is change the MCEL module's q output to be a reg so you can assign it an initial value, then give it and MPHSL's dout1 reg their values. For example:
// A Muller C-element
module MCEL (q, a, b);
input a, b;
output reg q = 0;
wire reset;
wire p1 = !(a & q);
wire q1 = !(b & q);
wire r1 = !(a & b);
always #* #13 q = !(p1 & q1 & r1);
endmodule
//Micropipeline stage (David Sutherland style).
module MPHSL(req_l, ack_l, req_r, ack_r, din,dout);
input req_l; output ack_l;
output req_r; input ack_r;
MCEL left(ack_l, req_l, !req_r);
MCEL right(req_r, ack_l, !ack_r);
// Data handling stage
input [7:0] din;
output [7:0] dout;
reg [7:0] dout1 = 0;
always #(posedge req_l) dout1 <= din;
assign dout = dout1;
endmodule
// Simulation wrapper
module SIMSYS();
wire req_1, ack_1;
wire req_2, ack_2;
wire req_3, ack_3;
wire req_4, ack_4;
reg tn;
initial begin tn = 0; #350 tn = 1; # 20 tn = 0; end
wire [7:0] d1,d2,d3,d4;
MPHSL s1(tn | req_4, ack_4, req_1, ack_1, (tn)? 8'hx5A: d4+1, d1);
MPHSL s2(req_1, ack_1, req_2, ack_2, d1, d2);
MPHSL s3(req_2, ack_2, req_3, ack_3, d2, d3);
MPHSL s4(req_3, ack_3, req_4, ack_4, d3, d4);
endmodule
And the result: