LDA is a simple opcode that loads to accumulator (register a) the pointed data in intel 8080 processor. In this condition (0x3a LDA addr) it says that op loads the addr to accumulator. But i couldn't recognize what it specifyies as addr.
A <- (adr) is the operation which 0x3a does and it uses 3 bytes of memory. I could store the data in the last 2 bytes of op as hi add and low add in a stack but accumulator is only 1 byte so i can't. Thanks.
LDA a16 instruction reads a byte from address a16 (the 8080 has a 16-bit bus) and stores that value into the A register.
This instruction is encoded as three : 0x3a lo hi, being lo and hi the two bytes that compose the address.
If you want to store an immediate (constant) value into A you should use instead instruction MVI A, x, being x the constant value. This instruction is encoded as: 0x3e x, only two bytes, as you seem to expect.
It looks like you are confusing memory address and memory content. The 8080 has an address bus of 16 bits and a data bus of 8 bits. That means that it can access memory from address 0x0000 up to 0xffff (16 full bits), or 65536 different addresses, but each of these address can store a single byte, with a value from 0x00 to 0xff (8 bits). That adds up to 64 kilobytes of memory.
Now, when you want to read a value from memory you need to specify the address of the value you are reading (remember, the address is 16 bits, the value is 8 bits). So you have to encode somehow the address into the instruction using 2 bytes. Intel CPU use the little-endian scheme, so to encode an address the lower 8 bits are stored in the first byte and the higher 8 bits in the second one. And that is what the LDA opcode does, and that is why it is 3 bytes long.
Related
I am confused on RGB565 and BGR565 color space in bits order. e.g, the hex value 0xF81E, I don't know at RGB565, R is high 5 bits in (0xF81E & 0xF800), or R is low 5 bits (0xF81E & 0x001F)
If you have a 16-bit value, then in RGB565 the R component will be the most significant 5 bits (ie high bits), whereas in BGR565 it'll be the least-significant 5 bits (low bits).
That said, if you are reading such 16-bit values from serialized bytes (eg a raw dump to file), then also consider the byte order of the serialization. For example, if the serialization isn't big-endian (network byte order), then 0xF81E appearing in adjacent raw bytes might indicate RGB565 value 0x1EF8.
In one of Intels IP Cores datasheet they do conversion from byte (0x17ff) to 32-bit (0x5ff) and I would like to know how they do that (from Parameter Editor Adress to Avalon-MM Address), an example would be great.
It's just a division by 0x100 (4), i.e. a bitshift to the right by two bits.
0x1800 / 4 = 0x600
0x3000 / 4 = 0xC00
Which makes sense, because 32 bits are four bytes. You'll see as well that there are four times as many byte addresses as there are 32-bit addresses for the same reason.
If I have say a 64-bit instruction, which has 2 bytes (16 bits) for opcode and the rest for operand address, I can determine that I have 48bits for the address (64-16). The maximum value that can be displayed with 48 bits plus 1 to account for address 0 is my go to number. This would be 2^48. However, I have the problem with the understanding of this in terms of the iB units.
2^48 is 2^40 (TiB) x 2^8 = 256TiB. But since TiB = 2^40 BYTES, when did the 2^48 become a BYTE? I generally believed that to get the number of bytes I'd have to divide by 8, but this doesn't seem to be the case.
Could someone explain why this works?
A byte is by definition the smallest chunk of memory which has an address. Whatever number of address bits, the resulting address is the address of a byte, by definition. In all (or at least, most) computer architectures existing today, a byte is the same as an octet, that is, eight bits; but historically there were popular computer architectures with 6 bit bytes, or 12 bit bytes, or even other more exotic number of bits per byte.
When a diagnostic tool is connected to the server it gets the the DTC.
I want to know how the DTC data is defined and stored in the ECU.
DTC codes are usually defined as 2-byte or 3-byte values.
A common representation following ISO 15031-6/SAE J2012 is as five-character alphanumeric code (ie. P0001) with the optional low-byte appended as hexadecimal value (ie. P0001-00). The first letter being either: P for Powertrain (00b, highest bits on highest byte), C for Chassis (01b), B for Body (10b) or U for Network related DTCs (11b). ie.
P0001 (Fuel Volume Regulator Control Circuit/Open) would be represented as bytes: 0x00 0x01
P0A01 (Range/Performance) would be represented as bytes: 0x0A 0x01
C0001 (TCS Control Channel A Valve 1) would be represented as bytes: 0x40 0x01
The DTCs are stored as their respective byte representation in Non-volatile memory (NvM) of the ECU, so that it can be retrieved even if the ECU has been power cycled. Along with the DTC additional information will be stored, i.e. Freeze frame/environmental data, DTC status mask (pendingDTC/confirmedDTC/...), counter (aging/debouncing), time of first occurence, etc.
"A memory has 1024 storage units with a width of 64. Suppose the memory is byte addressable. What is the address of the highest addressable memory position?"
Please correct me if I'm wrong.
byte addressable means individual bytes in a word have their own addresses.
there are 8 bytes in a 64 bit word.
therefore 8 x 1024 = 8192 addresses overall.
highest address therefore 8191.
I believe this to be true but am not a 100% sure. Please indicate where my logic falters if indeed it does.
I would say 1023.
There are 1024 storage locations, each numbered 0 to 1023, and each storage location holding 64 bits.
So you have a computer where a byte contains 64 bits. A byte is not 8 bits, but the minimum size of a memory location. All modern computers use 8 bits on a byte, but some older computers used 7, 9 og 14 bits on each byte.
But it's a really badly written question, because it does not define what a storage location is. So your interpretation might be right assuming a standard 8 bit in a byte cpu.