I have a design that has Xilinx FIFO IP. I am trying to verify the design using COCOTB based testbench. How can I include a Xilinx based IP for simulation using COCOTB? The simulation tool that I am using is Icarus.
Any help is much appreciated.
Do you already have Icarus set up so that you can compile your design without cocotb?
If so, take a look at one of the Makefiles under cocotb's examples/*/tests/ directory, copy one of them and fill out the variables so that it fits your design (see https://cocotb.readthedocs.io/en/latest/building.html#make-variables to see what they mean).
Then, make SIM=icarus should already do something useful.
Related
My task is to create a program to open and close an electronic valve that is plugged into GPIO ports on my BeagleBone, by using TTL signals.
Questions:
Can I do this?
How do I make an executable file to do this?
Can someone refer me to documentation on this?
Am I going about this in the wrong way?
Thank you.
P.S. If you couldn't already tell I am very new to this.
Yes
There are many ways. It's actually a pretty standard Linux computer and you can use any of a "million" different programming languages to achieve this. This also means you don't have to look for "Beaglebone" specific instructions (beyond the GPIO info below), but your problem is just "How do I write a program that can write text to a file on Linux?". Bonus: This sounds easy and it is easy!
Yes, take a look here for the hardware specific part:
https://github.com/adafruit/adafruit-beaglebone-io-python/issues/157
It describes fairly well both the new and the old sysfs interfaces you can use to manipulate GPIOs.
Depending on the language of your choice, there may already be bindings or a library to abstract this.
No (only based on the information you provided, are there other requirements?)
We all were new at this at some point, don't worry.
Sidenote: It's generally a good idea to make sure that you are running the latest firmware. In case of the BB-Family you can find them here: http://beagleboard.org/latest-images
I have been asked to integrate a custom JPEG encoder kernel module to the linux tree. The description is too generic. Can anyone suggest where in kernel tree should this go? I mean under what category in the drivers? I am assuming this is going to be compiled as a module and not statically linked to the kernel. If I generalize the question where should any custom kernel module live in the kernel tree? Assume the kernel module is a video/audio decoder/encoder. In this case it is a JPEG encoder as I said.
Any help will be highly appreciated.
Thanks.
When I posted this question I did not have clarity as how drivers are categorized and placed in the kernel tree. So explored and this is what I found so far:
If I am integrating/writing a new driver e.g. Ring Oscillator (this device simply generates some frequencies given a input period value, the frequency number is fed to a random number generator). To my understanding this should go under linux/drivers/misc/ whereas someone argued this should go under linux/drivers/misc/. But apart from that there seems to no strict rule where this kind of drivers should go. So it is quite up to your discretion and judgment where you ultimately place it. I have given the details of the steps involved here.
I also had to integrate a jpeg encoder and I was confused where this driver should go. I initially thought I will place it under linux/drivers/media/ as suggested in the comments. But this turned out to be a matter of preference. Finally I integrated it as a new buildroot package. In case you are interested I have described it here.
This is my understanding so far. If anyone thinks if I have missed anything please kindly point out.
Although it seems impossible from research:
Passing parameter to xci core
I am designing a custom core which uses an instance of a Xilinx FIFO. However, the top module has parameters which are exposed in the IP Packager, and should modify the included FIFO core.
module top();
parameter C_FIFO_DEPTH = 256
xilinx_fifo_core #(
.FIFO_DEPTH(C_FIFO_DEPTH)
) my_fifo_instance (...);
This way, when someone instantiates my module, by overriding parameter C_FIFO_DEPTH, they also change the embedded FIFO's depth.
Although this would work for user written modules, it doesn't work for instances of IP cores (xci), which seem to be configurable only through the "Customize IP" gui.
I have disabled Out-of-context generation, but still no dice.
I am currently working on a (very messy) solution using tcl scripts in the packaged core, however an elegant solution is desperately needed.
You can do this with the XPM_FIFO_xxx cores. Look in the UG953 Libraries Guide for docs and examples. You can also do it for RAM with XPM_MEMORY_xxx.
I can't think of any elegant solution, but here are three more messy ones:
(1) just use the largest FIFO you'll ever need. (Clearly likely to be a waste of area.)
(2) create a range of FIFOs of different sizes and use generate case to choose the right one. (Only any good if the range of useful sizes is reasonably limited.)
(3) don't use an IP block - design your own FIFO. (You probably thought of that.)
Could someone help explain what the differences are between the verilog code generated from the fsim directory of the rocket core (Top.DefaultFPGAConfig.v, using the default conf files provided) and the verilog code in the Zedboard folder (Top.DefaultFPGAConfig.v)? They are more or less of the same size, and look similar apart from a few changes which i couldnt quite understand the reason behind..
I am trying to synthesize it on a virtex 7 FPGA and not a Zynq based board, but just wanted help to understand what was different between the two sources for my knowledge.
Also, has anyone synthesized the fsim verilog code and run it with the testbench on an FPGA (non-Zynq based)?
The verilog included in the fpga-zynq repo should be the same as what the same config would produce inside fsim within rocket-chip because that is how it was generated. It is possible that if you use a newer version of chisel or rocket-chip to regenerate the verilog, you will get slightly different verilog. This is just a case of not committing to fpga-zynq as often as chisel itself is updated. Some of the updates to chisel tweak its internal passes, so it sometimes results in slightly different verilog output.
We have not tested the verilog on non-Zynq FPGAs. The verilog itself isn't that specialized, so I would expect most of the pain for getting it onto a Virtex 7 would be interfacing with it. I would definitely take a look at rocketchip_wrapper.v to get a feel for the external connections rocket-chip expects.
Sorry for Newbish question.
I am trying to learn about FPGA programming.
Before I spend $1K on a FPGA board:
if I just want to learn Verilog, can I run it entirely in Modelsim? (I realize there are some timing issues that only show up in actual chips; but for learning syntax / style of coding / ...)_
Thanks!
You can of course!
However, there are a few things that a simulator will let you away with that the FPGA compiler will not. Have a $FAVOURITE_SEARCH_ENGINE around for keywords like verilog coding styles synthesis.
See Resources for learning Verilog for some info on the differences between HDL programming and computer programming.
You most definitely don't need to splashout on a dev board if you are happy with just learning the language and simulating the results.
You can get the free Xilinx ISE Webpack which includes a basic version of ModelSim.
As you have mentioned simulation and testbenching is one aspect of FPGA design. Actually getting a design to work on real hardware is usually the more challenging part. However, just using software you can learn the language, get to grips with simulation and even synthesize your design to make sure it will meet timing and fit on a target device.
I would also suggest that $1K for your first dev board is quite high. I would start with something like the low-cost Xilinx Spartan-6 board, which is a tad under $300. You'll get a device with a decent amount of logic, memory and DSP slices for that.
If you're trying to learn Verilog there's no need to actually get an FPGA board (though, you can get FPGA development boards for much less than $1000 - you can get Xilinx's kit for $100). You can and should first learn Verilog using a simulator, though if you don't want to spend anything I'd suggest Icarus Verilog which is free (Open Source).
We had a hardware systems course in which some FPGA programming was done using VHDL. I downloaded ModelSim-Altera Software (starter edition available here)
We had FPGA boards in our lab, so it was easy to actually see your model behave. In your case, I would suggest:
Start modeling basic circuits like adder, decoders etc. In ModelSim you can also create and configure(characteristics like frequency of different signals) a test bench to verify (using timing diagrams) your model.
Once you are confident with the syntax and modeling, you can look for a lab around you which will allow you to get your hands dirty.
I hope this helps.
cheers
As others have noted, a simulator will get you a long way. There's nothing quite like flashing some real LEDs on and off though - wiggly waveforms on a screen just aren't the same :)
Many of the starter kits have VGA outputs so you can display your own pictures, which is always gratifying (I've found anyway!) $1000 is a lot to spend, try this Xilinx starter kit for $189 (which does have VGA), or this Altera starter kit (which doesn't).
Everyone above is right. However there is a synthesizable subset of Verilog and VDHL that can be used for actual hardware. For example $display can't be used. Recursion may be supported in some tools, as #Chiggs pointed out below. Keep that in mind when writing your code if it will ever be used in a chip. However the full language can be used in test benches.
No one mentioned www.edaplayground.com to learn SystemVerilog and/or VHDL. 100% free versions of the industry standard tools for simulation from the major vendors. Runs in the cloud. Nothing to download. Need email to register. Don't put your employers code up there; its on someone else's computer. There are example designs on the edaplaygroud site itself. Other sites have code examples that run on edaplayground, so you can run their code examples as a learning lesson by clicking one button. A list of verilog examples here: https://verificationguide.com/verilog-examples/
As others have stated there are aspects of FPGA & ASIC design that you will not learn in the simulation flow, specifically those related physical implementation but you can learn a lot from this approach, and it is very low cost (they want your email).
That being said edaplaygroud also has a synthesis tool.