Pass parameter during instantiation of ip core in vivado - verilog

Question

Although it seems impossible from research:
Passing parameter to xci core
I am designing a custom core which uses an instance of a Xilinx FIFO. However, the top module has parameters which are exposed in the IP Packager, and should modify the included FIFO core.
module top();
parameter C_FIFO_DEPTH = 256
xilinx_fifo_core #(
.FIFO_DEPTH(C_FIFO_DEPTH)
) my_fifo_instance (...);
This way, when someone instantiates my module, by overriding parameter C_FIFO_DEPTH, they also change the embedded FIFO's depth.
Although this would work for user written modules, it doesn't work for instances of IP cores (xci), which seem to be configurable only through the "Customize IP" gui.
I have disabled Out-of-context generation, but still no dice.
I am currently working on a (very messy) solution using tcl scripts in the packaged core, however an elegant solution is desperately needed.

Answer 1

You can do this with the XPM_FIFO_xxx cores. Look in the UG953 Libraries Guide for docs and examples. You can also do it for RAM with XPM_MEMORY_xxx.

Answer 2

I can't think of any elegant solution, but here are three more messy ones:
(1) just use the largest FIFO you'll ever need. (Clearly likely to be a waste of area.)
(2) create a range of FIFOs of different sizes and use generate case to choose the right one. (Only any good if the range of useful sizes is reasonably limited.)
(3) don't use an IP block - design your own FIFO. (You probably thought of that.)