How to generate RISC V toolchain for architecture without FPU? - riscv

Question

I am working on Rocket Chip and would like to simulate a processor without FPU and run programs on it. However I cannot find any complete information on which switches should I add to configure the RISC-V tools this way. Could anyone please help me?
From some partial information on different pages and forums I have tried a number of alternatives, including adding options --with-isa=RV64IMAC, --with-arch=RV64IMAC and --with-abi=64lp but most of the time the project yields "unknown option", so I am wondering if I'm using the right switches, or if I'm not missing something.
Among the switches that I've tried, the most successful is to add only --with-arch=RV64IMAC to riscv-gnu-toolchain:
Here is my build.sh (in riscv-tools directory):
build_project riscv-fesvr --prefix=$RISCV
build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=RV64IMAC
build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=RV64IMAC --disable-float
CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf
Before I added the switch --with-arch, this worked very well and I could simulate running my programs (with proxy kernel) on spike as well as on emulator and VCS.
Now the problem is that:
in this case the project riscv-tests doesn't build correctly, terminates by saying that it couldn't find the 'fma' function
Still with proxy kernel,I compile my programs as before, with adding options -msoft-float and -march=RV64IMAC. The executables would run without problems on spike, but on emulator and VCS they simply never end...
I think this is due to the build with RV64IMAC, since it's the only thing that I changed, but maybe I'm wrong. I would be grateful for any suggestions.

Answer 1

You can try to use compiler/linker keys:
CFLAGS += -march=rv64imac -mabi=lp64
LDFLAGS += -march=rv64imac -mabi=lp64
That should help you to generate code without hardware FPU and properly linked it with soft-fpu library.
Pre-built toolchain can be found here for an example:
http://gnutoolchains.com/risc-v/

Answer 2

Thanks for help everyone!
I think there were two problems for me:
Firstly, I didn't understand that the switches I add to the build.sh file are for configuration, so I could just have a look into the configure file of each RISC-V directory to see which switches are available and what they do.
Second, I probably didn't let my programs run long enough, because in comparison with the general architecture it was taking too much time and my logfile was becoming really big.
Excuse me please for these newbie problems...
If someone is interested, this is what I did at the end and what worked for me:
I used the IMA instruction set. I don't know if my problems were due to the C extension or if I did some other mistakes. In any case, this is what I use to generate the toolchain and other RISC-V tools:
build_project riscv-fesvr --prefix=$RISCV
build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=RV64IMA
build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=RV64IMA --disable-float
CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf
and I compile and link with the options:
-msoft-float -march=rv64ima
There should probably also be the -mabi=lp64 option but on my architecture this isn't supported, I have a bit older version of the repo...