Problem with creating structural modules using interfaces (SystemVerilog) - verilog

Question

I'm new in SystemVerilog, and currently learn interfaces, and I ran into problem with structural modules.
So, for example, i have created interface
interface BusInterface
#(parameter N = 3) (input logic i_clk);
logic i_RESET;
logic i_in;
logic counterClock;
logic[(N - 1):0] o_count;
logic o_ERROR;
modport DetectorInterface
(input i_RESET,
input i_in,
output counterClock,
output o_ERROR);
modport CounterInterface
(input i_RESET,
output o_count);
modport FallingsCounterInterface
(input i_RESET,
input i_in,
output o_count,
output o_ERROR);
modport StimulatorInterface
(output i_RESET,
output i_in,
input o_count);
modport MonitorInterface
(input i_RESET,
input i_in,
input counterClock,
input o_count,
input o_ERROR);
modport CommonInterface
(input i_RESET);
endinterface
I also created 2 modules:
module FallingEdge_Detector
(BusInterface.DetectorInterface interfaceDetector);
int k;
typedef enum logic[1:0] {s_NewCountCycle, s_ReadyToCount, s_EndCountCycle} stateType;
stateType currentState, nextState;
// Register logic
always_ff #(posedge interfaceDetector.i_clk, posedge interfaceDetector.i_RESET)
begin
if (interfaceDetector.i_RESET) currentState <= s_NewCountCycle;
else if (interfaceDetector.i_clk) currentState <= nextState;
end
// Next State logic
always_comb
begin
case (currentState)
s_NewCountCycle:
begin
if (interfaceDetector.i_in) nextState <= s_ReadyToCount;
else nextState <= s_NewCountCycle;
end
s_ReadyToCount:
begin
if (interfaceDetector.i_in) nextState <= s_ReadyToCount;
else nextState <= s_EndCountCycle;
end
s_EndCountCycle:
begin
if (interfaceDetector.i_in) nextState <= s_ReadyToCount;
else nextState <= s_NewCountCycle;
end
endcase
end
// Output logic
assign interfaceDetector.counterClock = (currentState == s_EndCountCycle);
assign interfaceDetector.o_ERROR = (currentState != s_EndCountCycle) &
(interfaceDetector.counterClock == 1'b1);
endmodule
module Counter
#(parameter N = 3) (BusInterface.CounterInterface interfaceCounter);
int k;
// Register logic
always_ff #(posedge interfaceCounter.i_clk, posedge interfaceCounter.i_RESET)
begin
if (interfaceCounter.i_RESET) k <= 0;
else if (interfaceCounter.i_clk) k <= k + 1;
end
// Output logic
assign interfaceCounter.o_count = k[(N - 1):0];
endmodule
The problem is that I cannot create a top-level module:
module FallingsCounter
#(parameter N = 3) (BusInterface.FallingsCounterInterface interfaceFallingsCounter);
/*
(input logic i_clk, i_RESET,
input logic i_in,
output logic[(N - 1):0] o_count,
output logic o_ERROR);
*/
logic counterClock;
FallingEdge_Detector Detector
(interfaceFallingsCounter.i_clk, interfaceFallingsCounter.i_RESET,
interfaceFallingsCounter.i_in,
counterClock,
interfaceFallingsCounter.o_ERROR);
Counter Counter
(counterClock, interfaceFallingsCounter.i_RESET,
interfaceFallingsCounter.o_count);
endmodule
When I try to make this in that way, i get the next errors:
Error (10285): Verilog HDL Module Instantiation error at FallingsCounter.sv(28): instance "Detector" specifies 5 actual port connections but module "FallingEdge_Detector" only expects 1
Error (10978): SystemVerilog error at FallingsCounter.sv(25): unknown type and interface type are not equivalent - equivalent types must have same number of bits
Error (10698): SystemVerilog error at FallingsCounter.sv(25): can't connect expression with incompatible data type to formal "interfaceDetector"
Error (10181): Verilog HDL Module Instantiation error at FallingsCounter.sv(25): too many ports used in Module Instantiation
Error (10181): Verilog HDL Module Instantiation error at FallingsCounter.sv(26): too many ports used in Module Instantiation
Error (10181): Verilog HDL Module Instantiation error at FallingsCounter.sv(27): too many ports used in Module Instantiation
Error (10181): Verilog HDL Module Instantiation error at FallingsCounter.sv(28): too many ports used in Module Instantiation
So, I have the question: how to create the top level module using interface?

Answer 1

You can't use modports in your top-level module port declaration unless they are going to be connected to the same modport in the lower level modules.
Modports are like sub-types passed through an interface port. They define access rights to a bundle of signals, and you cannot change the modport type one it is passed into the module.
What you can do is pass the full interface (without modports) through the top-level module