I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I dont get the same results. I used the 2 files generated after running 'make verilog' in vsim directory. For synthesis I defined the variable 'SYNTHESIS'. What are the things I might me missing go get appropriate results?
You should generate Verilog output first, incorporate it into your system or SoC and then pass it to Vivado as usual
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I'm newbie on Verilog.
In C Programming, build process are roughly as
- preprocessing - compile - assemble - linking
In Verilog, (BOOK : Verilog HDL: A guide to Digital Design and Synthesis), there is described Verilog development and build process are ...
- Design ( and simulation ) - Synthesis (elaboration, apply constraints and so on) - Verification
I think terms "synthesis" is most similar to compile.
But, "Verilog HDL: A guide to Digital Design and Synthesis" describes 'Compiler'(i.e., Compiler directive, `define, `ifdef, etc.)
Compile in Verilog means only for simulation target ?
You're comparing a C build process to elements of the engineering process of a Verilog project, so the terminology isn't going to match up. If you look at just the Verilog build process, it still won't necessarily match because it's quite different. Maybe you could view synthesis as analogous to compiling, mapping to assembling, and linking to placement and routing. But whether that analogy is useful depends on what exactly your goal is with this comparison.
I think you are confusing entirely different concepts. The Design, Synthesis, and Verification are stages representing different points in chronological time of a project. Those steps share a common source description, in this case Verilog HDL.
The compile step is part of a tool's process of reading that source HDL into a form that the tool can act upon. Both simulation and synthesis tool go through the compilation process which create an internal data structure most suitable to the task.
For the digital computer, there always has a halt mode which basically mean to turn off the system.
In the verilog, a $finish is used in verilog code.
I am just wondering how the synthesizer will synthesize this.
In Verilog ,commands that start with $ sign are called system functions(/task).
system functions are only called in simulation to control events and synthesis tools will ignore them. (depending on your synthesis tool some of them (e.g $readmem) may get synthesized.)
$finish terminates the simulation when called in simulation.
HDLs only provide a description of a designed hardware for simulation or (e.g. FPGA) synthesize porpuses. in the end, all the high-level codes of the RTL design must be translated(*synthesized) to a gate level circuit. So It's quite meaningless to think of it in a programming fashion and calling a function to mimic a hardware behavior.
I just started to learn Xilinx ISE. I wanna know what's the difference between Verilog Test Fixture and Verilog Module ? And when to use them?
Any help will be appreciated.
Thanks
I think I know where you are coming from but your question is not 100% accurate.
A test fixture is a piece of code to test another piece of Verilog code.
A module is a basic unit of hierarchy in Verilog.
What you are probably referring to is what I would call a hardware module: A module which can be converted to hardware.
The test fixture itself is never intended to be converted to working hardware and therefore can use the full power of the HDL language. It can contain non-RTL code.
A hardware module can only use the RTL subset of the HDL languge.
If we are talking about module in general then that distinction is no longer possible! The test fixture often is a module itself and can contain other modules. Those other modules can be hardware modules or other test modules. Most likely it will contain the hardware module it is going to test. (Often referred to as DUT: Device Under Test)
As to when to use them;
A test (module) is used to test other pieces of HDL code.
A hardware module is piece of Verilog code you intent to convert to hardware
If you look a This website. It is the only one I know that not only provides Verilog modules but also their testbenches.
I have compiled my benchmark and generated the .hex file.
where to include the .hex file in the verilog files.
all what I have for the verilog files are Top.DefaultVLSIConfig.v and memdessertMemDessert.DeafultVLSIConfig.v inside rocket-chip folder
I don't have vcs simulator in my os, can I take the verilog file and the hex file and do the simulation in another platform?
Haider
Yes, you can use another platform. On any platform you use, you will need a verilog simulator. Rocket Chip includes the verilog harness to use vcs, so if you use another simulator you may need to change the harness.
I would recommend using the C++ emulator Rocket Chip provides.
I don't have vcs simulator in my os
You can run your code using vcs simulator 2014.12 in EDAplayground
this isn't really a verilog question, it's a design dependent question, and partly a tool question.
there must be some memory definition somewhere in the code where you have to put a file reference to your hex file. should be pretty simple to find it.
Could someone help explain what the differences are between the verilog code generated from the fsim directory of the rocket core (Top.DefaultFPGAConfig.v, using the default conf files provided) and the verilog code in the Zedboard folder (Top.DefaultFPGAConfig.v)? They are more or less of the same size, and look similar apart from a few changes which i couldnt quite understand the reason behind..
I am trying to synthesize it on a virtex 7 FPGA and not a Zynq based board, but just wanted help to understand what was different between the two sources for my knowledge.
Also, has anyone synthesized the fsim verilog code and run it with the testbench on an FPGA (non-Zynq based)?
The verilog included in the fpga-zynq repo should be the same as what the same config would produce inside fsim within rocket-chip because that is how it was generated. It is possible that if you use a newer version of chisel or rocket-chip to regenerate the verilog, you will get slightly different verilog. This is just a case of not committing to fpga-zynq as often as chisel itself is updated. Some of the updates to chisel tweak its internal passes, so it sometimes results in slightly different verilog output.
We have not tested the verilog on non-Zynq FPGAs. The verilog itself isn't that specialized, so I would expect most of the pain for getting it onto a Virtex 7 would be interfacing with it. I would definitely take a look at rocketchip_wrapper.v to get a feel for the external connections rocket-chip expects.