I have a design that has Xilinx FIFO IP. I am trying to verify the design using COCOTB based testbench. How can I include a Xilinx based IP for simulation using COCOTB? The simulation tool that I am using is Icarus.
Any help is much appreciated.
Do you already have Icarus set up so that you can compile your design without cocotb?
If so, take a look at one of the Makefiles under cocotb's examples/*/tests/ directory, copy one of them and fill out the variables so that it fits your design (see https://cocotb.readthedocs.io/en/latest/building.html#make-variables to see what they mean).
Then, make SIM=icarus should already do something useful.
I have a FPGA project and theres a module written with Verilog in it,
I want to use it in an PCB Project, what should I do?
Usually you have to prepare your IP (verilog code) inside a package. In both Quartus and Vivado you have special interfaces to do just so.
See Xapp1168 for Vivado:
https://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf
I am learning Verilog with Altera's (now Intel) Quartus Prime development s/w and a DE0_Nano Cyclone IV dev board. I have the Charles Roth et al book "Digital Systems Design Using Verilog" which seems very good at the Verilog module level. I have also looked through a number of on line tutorials and I have a project working using a single Verilog file which is fine as far as it goes.
What I am missing and cannot find any guidance on is how to split a project into multiple hierarchical Verilog source files. I only want the hierarchy's top level file with the top level module instantiated in the Quartus project's .bdf file (the top level of the project drawn like a circuit).
Anyone any ideas how to do this? I presume simply including the lower level files in the top level Verilog file (via `include directive) is not the best way to do it. (Although do doubt it would work)
Help appreciated,
John
First, create your subcircuit (either in HDL or as a schematic/BDF file). Once your done, save it, and with the subcircuit file open, select File->Create/Update->Create Symbol Files for Current File.
Then, go to your top-level schematic, and click on the Symbol tool. In addition to the standard list of primitives, you should see a group of "Project" symbols. In there, you should find a block for your subcircuit to include in the top-level module.
Just add the Verilog files to the project: Project -> Add/Remove Files in Project... They will be compiled and instantiated as necessary.
Could someone help explain what the differences are between the verilog code generated from the fsim directory of the rocket core (Top.DefaultFPGAConfig.v, using the default conf files provided) and the verilog code in the Zedboard folder (Top.DefaultFPGAConfig.v)? They are more or less of the same size, and look similar apart from a few changes which i couldnt quite understand the reason behind..
I am trying to synthesize it on a virtex 7 FPGA and not a Zynq based board, but just wanted help to understand what was different between the two sources for my knowledge.
Also, has anyone synthesized the fsim verilog code and run it with the testbench on an FPGA (non-Zynq based)?
The verilog included in the fpga-zynq repo should be the same as what the same config would produce inside fsim within rocket-chip because that is how it was generated. It is possible that if you use a newer version of chisel or rocket-chip to regenerate the verilog, you will get slightly different verilog. This is just a case of not committing to fpga-zynq as often as chisel itself is updated. Some of the updates to chisel tweak its internal passes, so it sometimes results in slightly different verilog output.
We have not tested the verilog on non-Zynq FPGAs. The verilog itself isn't that specialized, so I would expect most of the pain for getting it onto a Virtex 7 would be interfacing with it. I would definitely take a look at rocketchip_wrapper.v to get a feel for the external connections rocket-chip expects.
Anyone knows good environment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?
You're stuck with either vendors tools, which are spotty at best on Linux (though my experience with Alteras utilities are somewhat better than with ISE).
However, if all you want to do is run your testbed, not actually synthesize anything, ghdl will be of use.
As mentioned by Arpan (almost) every VHDL simulator is supported by Linux, but they are usually very expensive. Your best shot would be to use one of the following:
Altera DS Web edition (Linux support has just been added) which comes with a free version of ModelSim.
Symphony EDA Sonata 3.1 is available as a free version with limited support.
Xilinx ISE which comes with Xilinxs own simulator: ISim.
Just to add an update to this: Xilinx Vivado has now been released with Linux support for ubuntu/debian and (I believe) redhat/centos.
The software is free for a range of the smaller devices and more common IP cores and includes a mostly decent simulator that is integrated into the tools and is also free.
It has a pretty steep learning curve, as do most of these tools, but as far as software in this industry goes, they've really done a good job with it.
If you prefer open source tools, look into http://www.cliftonlabs.com/vhdl/savant.html - vhdl does not have too many options in the FOSS space currently. If you are opting for vendor tools, all vendors would do Linux version of their simulators. Modelsim is a personal favorite due to the easy-to-debug features that it sports.
For a coding environment, I usually use VIM with vhdl syntax checkers turned on. Sigasi apparently has a commercial IDE with fancy stuff as automatic code completion, on the fly syntax check etc.
Let us know if you have further questions.
Arpan
For coding vhdl, Emacs with vhdl-mode is a must. You can use advanced edition functions, view the structure of designs, manage architectures and configurations. You can setup for multiple simulators.
I use the modelsim from Altera's Quartus web edition. Beware if you use a 64 bits Linux, this version of modelsim is 32 bits only.
There is now QUCS (http://qucs.sourceforge.net/) as well. It is open source and based on FreeHDL.
It can be used to design and simulate circuits using a graphical interface. And it can also simulate VHDL. Although for this you must also design the circuit components on the graphical area.
This video shows it clearly:
https://www.youtube.com/watch?v=-RrQlzLsf18
I'm using the linux ppa on Debian Jessie and it works fine.
GHDL is a nice simulator for VHDL, and even works with some third-party libraries (for example, Xilinx UNISIMS).
If you combine it with gtkwave, you should have a full working VHDL simulator and waveform viewer.
GHDL also supports writing to .GHW waveforms, which are fantastic for small simulations, cause it does include (often) all of the signals on your design.
I've used them with standard RTL simulation, and also for post-synthesis simulation with Xilinx UNISIMs.
Both should be available in your Linux distro repository. If not, you can fetch them from:
GHDL: http://ghdl.free.fr/
GtkWave: http://gtkwave.sourceforge.net/