I made some tests in some EDA playground, to check what simulator tools are reporting when in a module some inputs are driven.
Here is eda playground link : https://www.edaplayground.com/x/5qK4
So from my experiment the only way the tool is reporting some error when doing such thing is using the var keyword when defining the input.
Can someone explain why there is difference between the three different way to declare the input ?
I guess that means you can do port coercion when declaring it as wire
I post the code here as well
module test(
input var logic a,
input logic b,
input c
);
assign a = 1'b0;
assign b = 1'b0;
assign c = 1'b0;
endmodule
This is an input variable of type logic:
input var logic a,
There's no debate about that because each is explicitly declared*.
Section 23.2.2.3 of IEEE 1800-2012 says (the port kind is var or wire):
If the port kind is omitted: — For input and inout ports, the port
shall default to a net of default net type. The default net type can
be changed using the `default_nettype compiler directive
Therefore, because the default default_nettype is wire, this is an input wire of type logic:
input logic b,
Section 23.2.2.3 of IEEE 1800-2012 also says:
If the data type is omitted, it shall default to logic except for
interconnect ports which have no data type
Therefore this is an input wire of type logic:
input c
Now it is certainly illegal to drive a variable from an assign statement if it is already driven from somewhere else, so this line is definitely no good:
assign a = 1'b0;
Because input a is definitely a variable - that is explicit. But if we change that to (say)
always_comb a = 1'b0;
then it's still no good, because the input is considered to be driving the variable a using an assign statement and, as we already know, it is illegal to drive a variable from an assign statement if it is already driven from somewhere else.
However, because b and c are nets (of kind wire), it is fine to drive them from more than one place, so these lines should be OK:
assign b = 1'b0;
assign c = 1'b0;
*No project was ever late because the typing too too long. Therefore, why not just do this?
Related
I'm a just starting to learn verilog , and I'm having trouble with some things. I've found a few resources to help, but there are some things which aren't clear and I need specified. I have code for a D Flip-flop below. And I understand how the declaration for in and out work. What I dont get is the register.
When it says out is the variable associated with it.Does this association mean, out is the register along with output? Or does it mean out is also the output for the register?
module DFF(quarter, in, out) ;
parameter n = 1; // width
input quarter ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] out ;
always #(quarter=1)
out = in ;
endmodule
In Verilog there are nets and there are variables. The most common kind of net by far is a wire, which you're probably familiar with. You can declare a variable using var, but most people say reg, because that is how it always has been done.
(In Verilog, but not in SystemVerilog), wires have to be driven by
assign statements
the outputs of instantiated modules
and variables have to be driven from
initial and always blocks.
Your output out is driven from an always block and so must be a variable. The line
reg [n-1:0] out ;
declares the output out as being a variable (rather than a wire).
In fact, you are using an old-fashioned way of specifying inputs and outputs. Since 2001, the way to do it is like this:
module DFF #(parameter n = 1)
(input wire quarter,
input wire [n-1:0] in,
output reg [n-1:0] out);
always #(quarter=1)
out = in ;
endmodule
This is the so-called ANSI form and, I think you would agree, is more sensible. I would advise using this form, not the old-fashioned form you are using.
BTW, you code is a bit strange. I'm not entirely sure what it's supposed to do, but this if you're expecting output to be driven by in when quarter is 1, I'd do it more like this:
module DFF // #(parameter n = 1) // you're not using parameter n
(input wire quarter,
input wire [n-1:0] in,
output reg [n-1:0] out);
always #(*)
if (quarter == 1'b1)
out = in ;
else
// IMPORTANT ! : what is out when quarter != 1 ?
// your current code would synthesise to a latch
// is that what you wanted? (And if so, are you
// sure that's what you wanted)
endmodule
initially verilog was though as a language which does behavioral types of operation on state variables (registers, reg) and connects them via nets. So, reg is a variable which is supposed to keep its value between operations, net is just a connection and has no state associated with it, i.e. wire. reg values can be calculated in procedural blocks, i.e. always block, wires can be connected only (using continuous assignments, assign statements (outside of the always blocks)).
There are different rules for using for regs and wires and different behavior of them in simulation, in particular around multiple drivers. See Matthew's reply for more info.
module InoutConnect(
.X1(internal),
.X2(internal)
);
parameter width = 1;
inout [ width - 1 : 0 ] internal;
endmodule // InoutConnect
In the above code what is the format used,
I know that while instantiating the module .x1 is use to match the variable name but what about module definition.
What does it mean here?
it is called explicit port declaration, meaning that the external world will know this port by its explicit names, X1 and X2 in your case, though internally the same port will be known as internal in your case.
So, in your example you connect both ports to the same internal variable (looks bad to me :)) Though, this is one of the possible uses, in particular if you need to identical output ports. The other example is remapping internal structs or arrays to multiple potrts:
module m(
output .arr1(array[2:0]),
output .arr2(array[7:3]),
input logic [7:0] input_array
)
logic [7:0] array;
...
always_ff #(posedge clk)
array <= input_array;
...
endmodule
So, above you can use your array as the whole internally, but it will have a different representation in the external world.
See 23.2.2.2 ANSI style list of port declarations for more info.
The InoutConnect module is used to create an alias between two different signal names. For example
wire [7:0] color;
wire [7:0] colour;
InoutConnect #7 a1(color,colour);
Now, color and colour are two names for the same signal.
SystemVerilog added the alias construct to do the same thing without needed to create a separate module.
Hi I have a simple verilog statements where I want to transfer value at real net to a wire using assign statement. However I see a wire at "x" all the time regardless of the value of a real variable. Here is a snapshot of a sample code with values annotated at time zero:
QN is a wire and real_QN is of type real.
Any ideas why QN is at "x" even though real_QN is at "0" ?
So for reference, the "real" type in not synthesizeable. Only mentioning it because it might be relevant. As such, this solution isn't synthesizeable either. But it should work in simulation. You can not just assign one to the other in this case. But there is a function that will do it for you.
real someReal;
reg [63:1]someReg;
initial begin
someReal = 21.0 ;
$display("someReal---->%f",someReal);
$display("someReg---->%b",someReg);
#1
someReg = $realtobits(someReal);
$display("someReg---->%b",someReg);
Let me know if that does not work for you.
When are we supposed to use reg and when are we supposed to use wire in a verilog module?
I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type."
What are procedural assignment statements?
I have thoroughly googled this but was not able to find a clear explanation.
Wire:-
Wires are used for connecting different elements. They can be treated as physical wires. They can be read or assigned. No values get stored in them. They need to be driven by either continuous assign statement or from a port of a module.
Reg:-
Contrary to their name, regs don't necessarily correspond to physical registers. They represent data storage elements in Verilog/SystemVerilog. They retain their value till next value is assigned to them (not through assign statement). They can be synthesized to FF, latch or combinatorial circuit. (They might not be synthesizable !!!)
Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.
Logic:-
As we have seen, reg data type is bit mis-leading in Verilog. System Verilog's logic data type addition is to remove the above confusion. The idea behind is having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable. Logic data type doesn't permit multiple drivers. It has a last assignment wins behavior in case of multiple assignments (which implies it has no hardware equivalence). Reg/Wire data types give X if multiple drivers try to drive them with different values. Logic data type simply assigns the last assignment value. The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this
logic a;
assign a = b ^ c; // wire style
always (c or d) a = c + d; // reg style
MyModule module(.out(a), .in(xyz)); // wire style
Procedural blocks refers to always, always_ff, always_comb, always_latch, initial etc. blocks. While procedural assignment statements refers to assigning values to reg, integer etc., but not wires(nets).
wire elements must be continuously driven by something, and cannot store a value. Henceforth, they are assigned values using continuous assignment statements.
reg can be used to create registers in procedural blocks. Thus, it can store some value.
reg elements can be used as output within an actual module declaration. But,reg elements cannot be connected to the output port of a module instantiation.
Thus, a reg can drive a wire as RHS of an assign statement. On the other way round, a wire can drive a reg in as RHS of a procedural block.
For clear idea about declaration of reg or wire, refer the image below:
So, whenever inferring to sequential logic, which stores/holds some value, declare that variable/port as reg. Here, Q is a reg inside a module, but while instantiating this module inside some other module, then this port must be connected to a wire.
Remember, wire can only infer to combinational logic, while reg can infer to either combinational or sequential logic.
Dave's blog is a good source for detailed information. For further information, refer to synthesizing difference and Verilog wire-reg links.
Simple difference between reg and wire is, the reg is used in combinational or sequential circuit in verilog and wire is used in combinational circuit
reg is used to store a value but wire is continuely driven some thing and wire is connected to outport when module initialization but reg is con not connected
I was wondering that if a wire is declared in a Verilog code, but it is not assigned any value, does Verilog treat its value as ZERO ?
For example, I see a code where:
wire start;
module_if my_module_if(.clk(in_clk), .start(start));
Can I assume that the value of "start" will be zero?
Is this an acceptable style for Verilog?
Nets (including wire) without an assignment will be initialized to 'z' (aka high-impedance).
But if you are trying to use "start" as some kind variable or state, then you should probably declare it as "reg" or "logic" (System-Verilog) rather than "wire" (which tends to be used more for interconnect).
Style-wise, it may be less error-prone for you and for the reader of the code to be explicit about the initialization of your logic. For example ...
logic start;
initial begin
start = 1'b0;
end