run Implementation error. it's my coding wrong? - verilog

Question

I'm got a error when running Implementation at vivado 2018.2
this is error detail Info:
[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
[Common 17-69] Command failed: Placer could not place all instances
and my codes is following:
`timescale 1ns/1ns
module fa_seq(a, b, cin, sum, cout);
input a, b, cin;
output reg sum, cout;
reg t1, t2, t3;
always
#(a or b or cin) begin
sum <= (a ^ b & cin);
t1 = a & cin;
t2 = b & cin;
t3 = a & b;
cout = (t1 | t2) | t3;
end
endmodule
module fa_top;
reg pa, pb, pci;
wire pco, psum;
fa_seq uf1(pa, pb, pci, psum, pco);
initial
begin: blk_only_once
reg[3:0] pal;
for(pal = 0; pal < 8; pal = pal + 1)
begin
{pa,pb,pci} <= pal;
#5 $display("pa,pb,pci = %b%b%b",pa,pb,pci,":::pco,psum=%b%b",pco,psum);
end
end
endmodule
thanks for your answer.

Answer 1

Check whether you have instantiated and connected all of the top level ports.
It looks like you synthesized your actual design AND your test-bench.
The test-bench is the top level module and has no ports so all logic is optimised away.
You should split your design in files which hold the RTL and files which hold the test-bench/simulation code. In Vivado you have to specify what type it is if you 'add a file' here is a screen shot:

Answer 2

Your code has a latch inferred. Moreover you have used both blocking and non-blocking assignment in the same always block.
always
#(a or b or cin) begin //Not all dependencies are mentioned
sum <= (a ^ b & cin); //Non-blocking assignment
t1 = a & cin;
t2 = b & cin;
t3 = a & b;
cout = (t1 | t2) | t3;
end
I suggest you to re-write the always block as shown below.
always
#(*) begin
sum = (a ^ b & cin);
t1 = a & cin;
t2 = b & cin;
t3 = a & b;
cout = (t1 | t2) | t3;
end
Actually you don't need an always block for the above combinational logic. Simply use assign statements.
module fa_seq(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
wire t1, t2, t3;
assign sum = (a ^ b & cin);
assign t1 = a & cin;
assign t2 = b & cin;
assign t3 = a & b;
assign cout = (t1 | t2) | t3;
endmodule
However an efficient way of writing a full adder code would be :-
module fa_seq(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign {cout,sum} = (a + b + cin);
endmodule