Connecting components in VHDL structural - components

Question

I am working in VHDL, trying to connect three components M88, A8, A16, but once I synthesize the circuit and look at the RTL Schematic none of the components are connected. For example, I want to connect the output of M88 'out_high' to the input A16 of component A16. I do this by defining a signal OUT_H. Below is the structural of the main circuit and the entities of M88 and A16. The library 'Mult8x8.Components' is where I've defined the components. None of the connections between the components I've defined work, but I believe that I'm doing the same mistake that I can't figure out.
Thanks
entity Structure is
Port (
Clock, RST, Start : in BIT;
IN1, IN2 : in BIT_VECTOR (7 downto 0);
RESULT8x8 : out BIT_VECTOR (15 downto 0);
Done : out BIT_VECTOR(3 downto 0)
);
end Structure;
architecture Structural of Structure is use work.Mult8x8_Components.all;
signal OUT_M1, OUT_M2: BIT_VECTOR(7 downto 0);
signal OUT_H, OUT_L, ADD_MIXout, result16: BIT_VECTOR(15 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0';
signal High: BIT := '1';
signal F, OFL, REGclr: BIT;
signal DD : BIT_VECTOR(3 downto 0);
begin
-- REGclr <= Init or RST;
RESULT8x8 <= result16;
Done <= DD;
M88 : Mult8x8 port map
(CLK => Clock, RESET => RST, Start => Start, input1 => IN1, input2 => IN2, out_high => OUT_H, out_low => OUT_L, out_mix1 => OUT_M1, out_mix2 => OUT_M2, DONE => DD );
A8 : Adder8 port map (A=>OUT_M1, B=>OUT_M2, Cin=>Low, Cout=>OFL, Sum=>ADD_MIXout(11 downto 4));
A16 : Adder16 port map (A16=> OUT_H, B16 => OUT_L, E16 => ADD_MIXout, Cin16 => low, Cout16 => OFL, Sum16 => result16 );
end Structural;
entity Mult8x8 is
Port(
CLK, RESET, Start : in BIT;
input1 : in BIT_VECTOR (7 downto 0);
input2 : in BIT_VECTOR (7 downto 0);
out_high : out BIT_VECTOR (15 downto 0) := (others =>'0');
out_low : out BIT_VECTOR (15 downto 0) := (others =>'0');
out_mix1 : out BIT_VECTOR (7 downto 0) := (others =>'0');
out_mix2 : out BIT_VECTOR (7 downto 0) := (others =>'0');
DONE : out BIT_VECTOR (3 downto 0)
);
end Mult8x8;
entity Adder16 is
Port ( A16, B16, E16 : in BIT_VECTOR (15 downto 0);
Cin16 : in BIT;
Cout16 : out BIT;
Sum16 : out BIT_VECTOR (15 downto 0));
end Adder16;

Answer 1

When you want to map several entities between them in an upper entity like you're doing there, you need to first define these entities in a separate file (what I supposed you did). Then, I recommend that, in the "top level" (your entity Structure) you need to instantiate them before the begin term of your architecture with a different terminology: component.
NB: This, obviously, only works if the sub entities are compiled in the same work library.
This is an example of how you should change your code. Note that you're missing the component Adder8 that you need to define like the two others.
use work.Mult8x8_Components.all;
entity Structure is
Port (
Clock, RST, Start : in BIT;
IN1, IN2 : in BIT_VECTOR (7 downto 0);
RESULT8x8 : out BIT_VECTOR (15 downto 0);
Done : out BIT_VECTOR(3 downto 0)
);
end Structure;
architecture Structural of Structure is
signal OUT_M1, OUT_M2: BIT_VECTOR(7 downto 0);
signal OUT_H, OUT_L, ADD_MIXout, result16: BIT_VECTOR(15 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0';
signal High: BIT := '1';
signal F, OFL, REGclr: BIT;
signal DD : BIT_VECTOR(3 downto 0);
component Mult8x8 is
Port(
CLK, RESET, Start : in BIT;
input1 : in BIT_VECTOR (7 downto 0);
input2 : in BIT_VECTOR (7 downto 0);
out_high : out BIT_VECTOR (15 downto 0) := (others =>'0');
out_low : out BIT_VECTOR (15 downto 0) := (others =>'0');
out_mix1 : out BIT_VECTOR (7 downto 0) := (others =>'0');
out_mix2 : out BIT_VECTOR (7 downto 0) := (others =>'0');
DONE : out BIT_VECTOR (3 downto 0)
);
end component ;
component Adder16 is
Port (
A16, B16, E16 : in BIT_VECTOR (15 downto 0);
Cin16 : in BIT;
Cout16 : out BIT;
Sum16 : out BIT_VECTOR (15 downto 0)
);
end component ;
begin
-- REGclr <= Init or RST;
RESULT8x8 <= result16;
Done <= DD;
M88 : Mult8x8 port map
(CLK => Clock,
RESET => RST,
Start => Start,
input1 => IN1,
input2 => IN2,
out_high => OUT_H,
out_low => OUT_L,
out_mix1 => OUT_M1,
out_mix2 => OUT_M2,
DONE => DD );
A8 : Adder8 port map
(A=>OUT_M1,
B=>OUT_M2,
Cin=>Low,
Cout=>OFL,
Sum=>ADD_MIXout(11 downto 4));
A16 : Adder16 port map
(A16=> OUT_H,
B16 => OUT_L,
E16 => ADD_MIXout,
Cin16 => low,
Cout16 => OFL,
Sum16 => result16 );
end Structural;
Another way to instantiate your entities without calling the component before is the following:
A8: entity work.adder8 port map (OUT_M1, OUT_M2, Low, OFL, ADD_MIXout(11 downto 4));
In this case, you don't need to specify the ports, they are taken in the order defined in the entity.