VHDL - Shifting std_logic_vector by 8 bits - text

Question

Now that I have managed to shift my text while writing, I want to implement another feature, scrolling the text 1 digit per second. So for example I will will write "STACK" from keyboard, and then when I toggle a pin it will start floating on the seven segment display. I am getting multiple clocks error as I expected. Now, I got over that error with a counter but the text is not scrolling properly, random characters appear on random locations.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
entity my_shifter is
port(clk : in std_logic;
doShift : in std_logic;--shift mode
Scan_Dav : in std_logic;--from keyboard module, new data
Data_in : in std_logic_vector (7 downto 0);--scancode of the key pressed
O1 : out std_logic_vector(7 downto 0);
O2 : out std_logic_vector(7 downto 0);
O3 : out std_logic_vector(7 downto 0);
O4 : out std_logic_vector(7 downto 0)
);
end my_shifter;
architecture bhv of my_shifter is
signal bytes : std_logic_vector(63 downto 0):=(others => '0');
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
signal shift : std_logic:='0';
signal flag : std_logic:='0';
signal first_letter: std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
variable var:integer range 0 to 50000000 :=0;
begin
if rising_edge(clk) then
if var = 50000000 then
var:=0;
flag<='0';
shift <= '1';
else
flag <= '1';
var:=var+1;
shift <= '0';
end if;
end if;
end process;
process (clk, doShift)
begin
case doShift is
when '0' =>
if rising_edge(clk) then
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
end if;--till here it works fine.
when '1' => -- this is where it messes up
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>--ignore here
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end process;
O1 <= bytes(31 downto 24);
O2 <= bytes(23 downto 16);
O3 <= bytes(15 downto 8);
O4 <= bytes(7 downto 0);
end bhv;
I wonder how I can overcome this issue? What or where is the error?

Answer 1

Most likely you can get away with this working if you make your second process a sane clocked process.
Something like:
process (clk)
begin
if rising_edge(clk) then
case doShift is
when '0' =>
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
when '1' =>
if (shift = '1' and flag = '0' ) then
first_letter <= bytes(bytes'high downto bytes'high-7);
bytes <= bytes (bytes'high-8 downto 0) & first_letter;
end if;
when others =>
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end case;
end if;
end process;