I have an input voltage of 230V 50Hz which runs through a transformer the output of which is a 50A 50Hz current, i need to create and control a phase shift. Can it be done ?
The solution can be digital or analog and the phase shift can be introduced before or after the transformer.
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My simplified Simulink model involves plotting a sine wave going through an enabled subsystem. The simulation time step is 1/(125e6) seconds and the subsystem is only enabled once every 1/(250e3) seconds using a pulse generator. When the subsystem is disabled then the input sine data is 'lost' which is why the output looks like a jagged sine wave in the picture.
I need a way to pause the input data from flowing when the subsystem is disabled so that no sine data is 'lost'. The result should look like a very spread out sine wave. A simple way to accomplish this is to make the sine wave output at a frequency of 250kHz so that it's perfectly synced with the enabled subsystem, but this is not possible for my application.
I need to use an upsample block that has an upsample factor = 125e6/250e3 = 500. This will pad out my sample with an exact amount of 0's so that no data is missed when the enable block is disabled.
I'm having a problem in Quartus II v13 with a simple circular shift register. When I look at the logic with the RTL Viewer it is correct, but the circuit does not function correctly on the dev board. When I look at the Technology Map Viewer (Post-Fitting) I see that the clock only goes to stage zero of the shift register, the remaining stages are fed by the same clock via a CLKCTRL block. Sometimes re-arranging the circuit removes this block and then the circuit then functions correctly. What am I doing wrong?
I've used Enterprise Architect (EA) to create pretty drawings and I've liked it for that purpose. I find that I have a lack of understanding on how diagram elements link between one another. What I find particularly frustrating is that there is very little documentation on how this linking works (although lots of documentation on how to draw pictures).
I would like to create a model of a simple processor/ECU (electronics control unit). Here is the behaviour:
An ECU has an instance of NVRAM (which is just a class) for an attribute
An ECU has a voltage supply (an analog value representing the voltage level supplied to the ECU)
An ECU has two digital input ports
Each digital input port fires signals when its value changes
the ECU has a state machine with three states; the state machine enters state 1 on entry; the state machine transitions to state 2 on a firing of either digital input ports so long as the ECU voltage supply is greater than 10 V
the ECU exists to state 3 when Voltage drops below 8; and goes back to normal processing when Voltage rises above 9
Can you develop a model that demonstrates how these elements interact? (Is there some reference I can read on how to understand this approach?)
Here's my first attempt:
State Machine
I used a composite diagram in the ECU state so that I could have access to the digital ports diagramatically. I created a link for each port so that they "realize" class input PIn. I assume I can depict class attributes this way.
I "create a link" so that the DIO triggers realize the DIO ports. Not sure I can do this.
The class state machine is where I get lost. Not sure on how to create a trigger for ECU.Voltage < 8.
I am using the Spartan 3e Xilinx FPGA board, and I am trying to sync two FPGAs to generate the same sine wave. Due to limited I/O pins there is only one connection from the Master to Slave. Is there a way to sync them up and set the phase of the sine wave?
For example when the master hits zero phase a flag raises and the slave is set to zero phase too.
The function prototype of the sine lut is given below. I am just starting out so any help is appreciated thank you.
sine sine_lut (
.ce(clock_enable), // input ce
.clk(CLK_50MHZ&& clock_enable), // input clk
.sclr(!clock_enable),
.pinc_in(line_freq[31:0]), // input [31 : 0] pinc_in
.poff_in(0), // input [31 : 0] poff_in
.sine(sine_generate[12:0]), // output [12 : 0] sine
.phase_out(phase_out) // output [31 : 0] phase_out
);
The method mentioned in the question would work to some extent:
If the jitter of the clocks is not that big to cause a significant desynchronisation during the period of the sine wave
If some discontinuity in the slave output is tolerable.
In order to overcome the discontinuity you can modify the method as following. Instead of just resetting the waveform, simply readjust the frequency of the signal on the slave to be slightly higher or lower for the next period, depending on whether it is too fast or too slow. You can do this using PID control technique, for example (the adjustment will be proportional to the phase error). Or simply recalculate the frequency based on the measured time between sync pulses.
If the sine wave frequencies are much slower than the clock frequency, you can utilise the PWM technique to encode the sine values of the master as a signal Duty Cycle, measure it on the slave and output the same value. A very small phase shift is expected, but again, it shouldn't be noticeable if the clock is much faster than the sine.
I have a adc module on my board. I create a sine wave on signal generator. And I give output of this generator to a adc pin. Finally I read value of this pin periodically. I try to create a sine wave on my software.
x = t,
y = Asin(wt),
A : amptitute value of the generator,
w : 2πf, f : I set its value on my software.(difference time between two read operation)
t : time
And I don't use value of adc pin. Isn't this value important to create wave?
I will try to provide you with some hints based on what I understood from your post.
The ADC is supposed to sample the analogue signal generated at a defined frequency in order to yield a digital signal. In your case, you need two information to trace your curve:
Data:
data to be traced (samples) which represents the amplitude of the signal all along sampling time (at each sampling instant).
Time:
you need to know the period in time at which ADC is sampling the signal then associate each data with its corresponding instant in time. Period can be deduced from the frequency at which ADC samples signal T = 1/f.
ADC stores each sampled data in a register and an interrupt would be generated to notify processor about a new coming data. Your interrupt service routine (in case you are proceeding with interrupts) must be able to extract that data before it will be replaced by the next sample. As a suggestion, you may create a buffer within your application where your interrupt routine could store data in it. Then, your application can extract data from buffer and use it to draw the curve if your system has a display output or send it to a desktop application that will do the job.
You don't need to stick to the equation in your post; it is for analogue. Rather you can think of the digitized curve as f(t) = Data(t).
As you are using linux, if you don't want to deal with interrupts you may proceed with reading data using /sysfs interface. Note that opening a file to read data for every single sample could be slow depending on your application requirements.