Is there any difference between
wire A = B & C;
and
wire A;
assign A = B & C;
?
I do not think so but I have seen code using the latter and I wonder if that was done for a reason.
They are functionally the same in your example. There are slight differences when adding a delay to a wire declaration.
wire #5 A = B & C;
wire A;
assign #5 A = B & C;
In the first form, the delay gets added to all other net drivers. You can also use SDF back annotation to modify the wire delay.
In the second form, the delay applies to only that continuous assignment, and you cannot use SDF back annotation to modify the delay.
My observation is that most people use the second form in RTL to keep the declarations and functionality separated.
Related
I am trying to create a 4-bit multiplier using behavioral Verilog with assignment statements and procedural blocks if possible. The circuit I am trying to replicate is this one :
So far, I defined the submodule fouralu_adder which is a simple unsigned 4-bit adder. Then I wrote the following psuedo-code:
module fouralu_multi(
input [3:0] A_i,//Input signals
input [3:0] B_i,
output [7:0] S_o//Output signal
);
wire [4:0] S1,S2;//These were supposed to be the SUM wires coming out of AD1 and AD2
wire [3:0] AND;
fouralu_adder AD1(
//Port connections here
);
fouralu_adder AD2(
//Port connections here
);
fouralu_adder AD3(
//Port connections here
);
endmodule
The initial idea I had was to somehow assign the behavior of the and gates with something like :
assign AND = A_i&B_i[0]; then repeat for each value of B_i but quickly realized it would be quite an inefficient approach. This leads me to ask the question : How do I implement the circuit using behavioral verilog? How am I to connect the input ports to the submodule without using structural verilog, and with as little wire variables as possible? Thank you in advance for your help
You can use for loop, google it and you'll learn how to use it.
For example
integer idx;
reg [3:0] A_AND_B [0:3];
always #(*)begin
for( idx=0; idx<4; idx=idx+1) A_AND_B[idx] = {4{B[idx]}} & A;
end
this code equals to
reg [3:0] A_AND_B [0:3];
always #(*)begin
A_AND_B[0] = {4{B[0]}} & A;
A_AND_B[1] = {4{B[1]}} & A;
A_AND_B[2] = {4{B[2]}} & A;
A_AND_B[3] = {4{B[3]}} & A;
end
I'm trying to understand how many flip-flips would this code produce when synthesized?
I've got 2 test cases with non-blocking and blocking assignment code.
Test 1.
wire aclk;
wire [1:0] a;
reg [1:0] c;
reg [1:0] b;
always #(posedge aclk)
begin
b <= a + 1;
c = b;
end
Test 2.
wire aclk;
wire [1:0] a;
reg [1:0] c;
reg [1:0] b;
always #(posedge aclk)
begin
b = a + 1;
c <= b;
end
The Test 1 has 4 FFs and Test 2 has 2 FFs.
I can't understand how does it make a difference I just switching the code.
Thanks for letting me know at all.
They are functionally different. Non blocking assignment evaluate the right hand side and then continue to the next statement, storing into the left hand side isn't done until all other statements are evaluated first. Blocking statements evaluate the right hand side and store it into the left hand side immediately.
Test1 is doing this:
evaluate (a+1)
store b into c , BEFORE (a+1) is stored into b!!!
store (a+1) into b
Test2 is doing this:
evaluate (a+1)
store (a+1) into b
store b into c
Like toolic mentioned, you generally used non-blocking statements in sequential logic. Most people also recommend not mixing non-blocking and blocking statements in the same begin-end block.
I have a circuit whose truth value looks like this A =BC+^C[(B and C) or (not C)]
Here I give,
output A;
input B, C;
wire w1, w2;
and (w1, B, C);
not (w2, C);
or (A, w1, w2);
My question is why do we write input B, C; Can we write it as reg B, C;?
What exactly is the difference?.
You are not showing a complete example, but inputs and outputs are part of a hierarchical module declaration. reg is a data type associated with a signal. Typically one encapsulates your circuit in a module, and then you instantiate that module in a top-level module to provide stimulus and observe the outputs.
module circuit( output wire A;
input wire B, C;
wire w1, w2; // internal wires
and (w1, B, C);
not (w2, C);
or (A, w1, w2);
endmodule
module top;
reg B,C; // these are different signals that get connected to the circuit wires
wire A;
circuit c(A,B,C);
initial begin
B = 0; C = 0;
...
endmodule
comparing input and reg is similar to comparing a keyboard to a verilog code. input defines a direction of a port. reg defines a data type.
However, every port has a data type associated with it. Default data type for an input/output port is wire. So input B is the same as input wire B.
Now, the right question is: what would be a differnce between wire and reg.
wire is a data type for describing connection between module instances. Its main characteristic is that it should always be connected and cannot keep is state otherwise. reg can keep the state if not connected. There are multiple differences in usage which you can find in corresponding verilog tutorials.
In the following code:
wire a;
reg b;
assign a = b;
ModuleName foo(a, other wire inputs, ... , wire outputs);
Assume that they are part of a top level module.
I wanted to run an always# block but make changes in the input of a module instantiated in this module.
always#(*) b = c^d; //Some Logic
The thing is, they are wires and cannot be on the LHS in an always# block. Can I make changes to band expect to see them in a i.e. the input of the Module foo.
Yes. Every time you change b, a will change too. That is what an assign statement does. Remember this is hardware. The statement
assign a = b;
means 'drive wire a with whatever value reg b has for all time'.
I would like to know if there is a syntax in Verilog to access a wire in a sub-module without making that wire an output.
For example, if have the following modules:
module Module_Sub(a,b);
input a,b;
wire c;
...
endmodule
module Module_Top(d, e);
input d,e;
wire f;
Module_Sub sm(d,e);
...
endmodule
Now, I want to access the wire 'c' in the instance 'sm' from the scope of Module_Top.
Is there a way to do it?
maybe something like:
assign f = sm/c;
(This syntax obviously didn't work for me).
P.S:
I know this isn't the best practice, but in my case it will make things a lot easier.
Thanks!
edit: I want it for a synthesis-able code.
You were very close. Use dot, not slash:
module Module_Sub(a,b);
input a,b;
wire c;
endmodule
module Module_Top(d, e);
input d,e;
wire f = sm.c;
Module_Sub sm(d,e);
endmodule
Refer to IEEE Std 1800-2012, section 23.7 "Member selects and hierarchical names".