The following code is written for an asynchronous counter. The program compiles fine but the counter value doesn't increment after 1. What am I doing wrong?
Here is the code:
//TOP
module CounterWithDivider(clk,reset,temp,q);
input clk,reset;
output [3:0]q;
output reg [3:0]temp;
reg [3:0]clkDivider;
TFF a(clkDivider,clk,reset,q[0]);
TFF b(clkDivider,q[0],reset,q[1]);
TFF c(clkDivider,q[1],reset,q[2]);
TFF d(clkDivider,q[2],reset,q[3]);
always #(posedge clk or negedge reset)
begin
if(~reset || clkDivider==12)
clkDivider<=0;
else
if(clk)
begin
clkDivider<=clkDivider+1;
temp<=clkDivider;
end
end
endmodule
// T flip flop
module TFF(clkDivider,clk,reset,q);
input clk,reset;
input [3:0]clkDivider;
output reg q;
always #(posedge clk or negedge reset)
begin
if(~reset)
q<=0;
else
if(clkDivider==11)
q<=1;
end
endmodule
A T-FlipFlop, or toggle flop should toggle its output when enabled, you just have:
if(clkDivider==11)
q<=1;
Replace q<=1 with q<=~q to make it toggle when enabled.
As you mentioned, this is an asynchrous counter. The reason your Verilog simulation is not doing what you want is that TFF instance b is trying to sample its data input (clkDivider) using a different clock signal. clkDivider is clocked by signal clk, but you are trying to sample it using a different clock signal (q[0]).
You need to either find a way to synchronize the clkDivider signal into each of the other 3 clock domains, or use a fully synchronous design.
Related
I am quite new to verilog and active-hdl. I have got a problem and I would appreciate it if someone could advise me on this.
I can't see the waveforms of second layer modules on waveform viewer. More precisely, the signals in submodules show either Z or X.
Please note that I have enabled read/write access through tools/preferences/simulation/ access design object.
For example I am generating a clk in tb module and connect it to clk_mod, trying to see the clk in clk_mod, however for clk it shows only "Z" and for "i" only "X".
`timescale 1ns/100ps
module tb;
reg clk;
clk_mod dut(.clk(clk));
initial
begin
clk = 0;
forever
#5 clk = ~clk;
end
endmodule
module clk_mod (input clk);
reg i;
always #(posedge clk)
begin
i=10;
end
endmodule
I think that your tb is lacking exit from simulation. you should add the following statement to the tb module (as a separate statement):
initial #20 $finish;
This would finish simulation at step 20 and should create waveforms for you, if you use right tools.
Also, you declared i as a single-bit reg, so, you cannot fit '10' in to it. So, your waveform should show toggling clock and a single transaction of 'i' from 'x' to '0'.
I guess you should have declared 'i' as this:
reg [3:0] i;
I am trying to implement the I2S Transmitter in verilog. The datasheet for it is at: https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
I wrote the code, but my SD line is delayed 1 clock cycle when i test it.
Can someone check my implementation?
module Transmiter(
input signed [23:0] DLeft, input signed [23:0] DRight, input WS, input CLK,
output reg SD
);
wire PL;
reg Q1,Q2;
reg [23:0] shift_reg;
reg [23:0] Tdata;
assign PL = Q1^Q2;
always #(posedge CLK)
begin
Q1 <= WS;
Q2 <= Q1;
end
always #( Q1) begin
if (Q1)
begin
Tdata <= DRight;
end
else
begin
Tdata <= DLeft;
end
end
always #(negedge CLK)
begin
if(PL)
begin
shift_reg <= Tdata;
end
else begin
SD <= shift_reg[23];
shift_reg <= {shift_reg[22:0],1'b0};
end
end
endmodule
EDIT: here is a image of waveform image
TEST BENCH CODE:
module Transmitter_tb(
);
reg CLK, WS;
reg [23:0] dataL;
reg [23:0] dataR;
wire SDout;
Transmiter UT(dataL, dataR, WS, CLK, SDout);
initial begin
dataL = 24'hF0F0FF; #2;
dataR = 24'h0000F0; #2;
end
always begin
CLK=0; #20;
CLK=1; #20;
end;
always begin
WS=0; #1000;
WS=1; #1000;
end;
endmodule
Your negedge block contains an if-else construct and will only ever compute one or the other on a single clock edge. SD will therefore not change value when PL is high.
Furthermore you are using non-blocking assignments(<=) in your code. This roughly means that changes won't be evaluated until the end of the always block. So even if SD <= shift_reg[23] after shift_reg <= Tdata it will not take on the new value in shift_reg[23] but use the previous value. If you want SD to change immediately when shift_reg[23] changes you need to do this combinatorically.
This should work:
always #(negedge CLK)
begin
if(PL)
begin
shift_reg <= Tdata;
end
else
shift_reg <= {shift_reg[22:0],1'b0};
end
assign SD = shift_reg[23];
Working example: https://www.edaplayground.com/x/4bPv
On a side note I am still not convinced that DRight and DLeft are in fact constants, I can see that they are in your TB but it doesn't make sense that the data for your I2S is constant. Your current construct will probably generate a latch(instead of a MUX), and we generally don't want those in our design.
You should clean up your use of blocking versus non-blocking statements:
Always use non-blocking assigments, meaning "<=", in clocked statements.
Always use blocking assigments, meaning "=", in combinational (non-clocked) statements.
This is a industry-wide recommendation, not a personal opinion. You can find this recommendation many places, see for instance:
http://web.mit.edu/6.111/www/f2007/handouts/L06.pdf
The sensitivtity list being incomplete (as pointed out by #Hida) may also cause issues.
Try to correct these two things, and see if it starts working more as expected.
Also note that you are using Q1 (among other signals) to generate your PL signal. If the WS input is not synchronous to your local clock (as I assume it is not), you need to put one more flop (i.e. two in series) before starting to use the output, to avoid metastability-issues. But you won't see this in an RTL simulation.
As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:
module Addr_8bit(Clk, Rst, En, LEDOut
);
input Clk;
input Rst;
input En;
output reg [7:0] LEDOut;
always #(posedge Clk or posedge Rst) begin
if(Rst)
LEDOut <= 8'b00000000;
if(En)
LEDOut <= LEDOut + 8'b00000001;
end
endmodule
The error is on the line where the non-blocking assignment: LEDOut <= LEDOut + 8'b00000001; is located.
Particularly it says that:
ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).
Thank You.
Change your behavioral description (the code inside the always block) as follows:
always#(posedge CLK or negedge RST) begin
if(!RST) begin // Reset condition goes here
LEDOut <= 0;
end
else begin // Everything else goes here
if(En)
LEDOut <= LEDOut + 1'b1;
end
end
The reason your code won't synthesize is because you generally can't assign to the same register under the same edge of two different signals. (You can't have your always block trigger on the low to high transition of CLK and RST if you're assigning to a variable in both cases.) So you can't trigger the reset condition on the positive edge of RST, but you can do it on the negative edge. This is due to the way the physical register elements (called flip-flops) are designed.
i want to shift a signal by fixed number of clock cycles. I receive the signal from adc. kindly let me know how to implement this
HINT: Not a full answer
A 8 bit flip-flop in verilog might look like:
reg [7:0] a;
always #(posedge clk, negedge rst_n) begin
if (~rst_n) begin
// Active Low Reset condition
a <= 'b0;
end
else begin
a <= input_eight_bit;
end
end
To delay for multiple clock cycles you need multiple flip-flops feeding from one to the next. This creates a pipe line or delay line.
Removing #2 reset after monitor statement makes the code not to work.The output just stands at 0 x. Whereas including it works fine. Why?
module counter(out,clock,reset);
input clock,reset;
wire clock,reset;
output [3:0]out;
reg [3:0]out;
always #(posedge clock or negedge clock)
begin
if(reset)
out<=1'b0;
else
out<=out+1;
end
endmodule
module tb();
reg clock,reset;
output [3:0]out;
counter c(out,clock,reset);
initial
begin
clock=0;
reset=1;
end
initial
begin
$monitor("%d %d",$time,out);
#2 reset=0;
end
always
#1 clock=~clock;
initial
#100 $finish;
endmodule
By removing the #2 you create a race condition on reset:
initial reset = 1;
initial reset = 0;
Simulators will often have the the final value of reset the last assignment read in the compiling order. Try merging you initial blocks:
initial
begin
$monitor("%d %d",$time,out);
clock=0;
reset=1;
#2 // <-- optional (and still recommened) if you make the below change
// #(clk) //<-- if you truely want a dual edge triggered flip-flop with synchronous reset
reset=0;
end
Dual edge triggered flip-flop are very uncommon and many synthesizers and FPGAs do not support them. I'm guessing you are intending to have an negative edge triggered flip-flop with an active high asynchronous reset. In this case replace:
always #(posedge clock or negedge clock)
with:
always #(negedge clock or posedge reset)