module tb_alu32();
reg clk, reset;
reg [31:0] tb_a, tb_b, tb_yexpected;
reg [2:0] tb_op;
wire [31:0] tb_result;
reg[31:0] vectornum, errors;
reg[99:0] testvectors[10000:0];
...
always
begin
clk=0;#5;clk=1;#5;
end
$readmemh("C:/altera/13.0/practice/week3/alu32/testvect.tv",testvectors);
always # (posedge clk)
begin
#1; {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];
end
endmodule
I read testvect.tv but tb_a and tb_b's MSB are missing and LSB is set 0 like
0000_0001->0000_0002
0000_0002->0000_0004
FFFF_FFFF->FFFF_FFFE
FFFF_FFFE->FFFF_FFFC
8000_0001->0000_0002
How can I solve this?
If I use readmemb, it works well.
If I assign values it works well.
Why did it happen?
This is what is causing the error
Your {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];
LHS is 99 bits and RHS is 100 bits. Just declare
reg[98:0] testvectors[10000:0];
i.e instead of 100 bits, declare testvectors to be 99 bits.
Related
I am trying to delay a 32-bit signal using shift register. My logic is a single flip flop delay a signal by 1 clk so I use shift register as it is combination of flip flop can someone guide me what is wrong with this code.
module delay_n_cycles (
input wire [31:0] data_in,
input wire clk,
output reg [31:0] data_out,
parameter N = 5
);
reg [31:0] shift_reg;
always #(posedge clk) begin
shift_reg <= {shift_reg[30:0], data_in};
if (N == 0) begin
data_out <= shift_reg[31];
end else begin
data_out <= shift_reg[N-1];
end
end
endmodule
First of all, your code is syntactically wrong. parameter cannot be declared in a way you provided.
Your shift register is only 32 bit wide. Usually, to delay multi-bit data this way, you need to keep N copies of data in the register, shift them at one end and read at the other. I guess the following should help:
module delay_n_cycles #(parameter N = 5)(
input wire [31:0] data_in,
input wire clk,
output reg [31:0] data_out
);
reg [N-1:0][31:0] shift_reg;
always #(posedge clk) begin
shift_reg <= (shift_reg << 32) | data_in;
data_out <= shift_reg[N-1];
end
endmodule
This code will work with system verilog because it used packed multi-dimensional arrays.
You need to shift the reg by 32 (width of the data) in packed version.
Here is an example of a testbench:
module tb();
bit clk;
int clkCount;
initial
forever begin
#5 clk = ~clk;
clkCount++;
end
logic [31:0] data_in, data_out;
initial begin
$monitor("%0t (%0d) [%h]: %0d --> %0d", $time, clkCount, ds.shift_reg[4], data_in, ds.data_out);
for(int i = 0; i < 20; i++) begin
#10 data_in = i;
end
$finish;
end
delay_n_cycles ds(data_in, clk, data_out);
endmodule
I'm writing a verilog module for my CompSci class and this module specifically is the data memory module. Structurally and analytically, I'm looking at it and it should work based off of the other files that I have, but I'm not sure why this one specifically is acting up and giving me all x's. Hoping a fresh set of eyes can help find the error I missed. Thanks in advance.
datamem.v:
module datamem(Ina, Inb, enable, readwrite, dataOut, clk, rst);
input wire [31:0] Ina;
input wire [31:0] Inb;
input wire enable;
input wire readwrite;
input wire clk;
input wire rst;
reg [31:0] memory[0:65535];
output reg [31:0] dataOut;
always #(memory[Ina]) begin
dataOut = memory[Ina];
end
always #(posedge clk) begin
if(1'b1 == readwrite) begin
memory[Ina] = Inb;
end
end
endmodule
datamem_tb.v:
module datamem_tb();
reg [31:0] Ina;
reg [31:0] Inb;
reg enable;
reg readwrite;
reg clk;
reg rst;
wire [31:0] dataOut;
datamem DUT (Ina, Inb, enable, readwrite, dataOut, clk, rst);
initial
begin
Ina <= 32'd0;
Inb <= 32'd0;
enable <= 0;
readwrite <= 0;
#20 Ina <= 32'd1234;
#20 Inb <= 32'd1234;
#20 Ina <= 32'd0517;
#20 Inb <= 32'd10259;
end
always #(Ina or Inb)
#1 $display("| Ina = %d | Inb = %d | dataOut = %d |", Ina, Inb, dataOut);
endmodule
A few things as to why you are getting all 'x:
You never run the clock, you need to add something like the following to have the clock toggle:
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
You never assert readwrite which is required to write to your memory module (you set it to 0 on line 20 and never change it). Without being written to, memory will retain its original value of 'x for every element
Aside from that, there are a few other issues with your module:
Use implicit sensitive lists (instead of always #(memory[inA]) use always #(*))
Use non-blocking assignment for your memory write (memory[inA] <= inB)
Consider using $monitor instead of $display for your print statements to avoid timing issues, and you only need call it at the beginning of your initial block in your testbench (http://referencedesigner.com/tutorials/verilog/verilog_09.php)
Your rst and enable arent connected to anything.
Another example of a memory unit implementation can be found here:
Data memory unit
module ocircuit (ooutp,s0,s1 ,clk,write,raddA,raddB,wadd,wdata);
output [3:0] ooutp;
input clk, write,s0,s1;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
reg [9:0] ooutp;
wire [3:0] dataA;
wire [3:0] dataB;
reg [9:0] inner;
regfile y (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);
always #(posedge clk) begin
if (s0==0) begin
assign inner = dataA [3:0]*dataB [3:0];
end
else begin
assign inner = ((dataA [3:0]*dataB [3:0])+inner [9:0]);
end
//inner=inner1;
ooutp =s1?inner [9:0]:10'd0;
end
endmodule
This is the code. regfile is a simple register file. In the testbench, s0 = 0 during the first cycle and s0 = 1.
For subsequent cycles, this code should return the value of A*B+C*D by using one adder and one multiplier. In the first cycle, when c0 = 0, the answer that is saved in inner (a register) is right but in the second cycle, when c0 = 1 the answer is wrong.
Por example: A=1; B=2; C=1; D=1;
First cycle: x=A*B=2
Second cycle (C*D)+x=5
I think there is something wrong with this statement
assign inner = ((dataA [3:0]*dataB [3:0])+inner [9:0]);
Any help or hint will be appreciated.
Although assign can be used from within an always block, I think you just wanted to store a value into inner depending upon the value of s0. To do that, use non-blocking assignments ( <= ).
Also, you can directly output to ooutp instead of saving the final result in inner, avoiding a possible glitch in the multiplexer you instantiate here:
ooutp =s1?inner [9:0]:10'd0;
Which, by the way, it should be outside the always block, in an assign line:
assign ooutp = s1? inner [9:0]:10'd0;
module ocircuit (ooutp,s0,s1 ,clk,write,raddA,raddB,wadd,wdata);
output [3:0] ooutp;
input clk, write,s0,s1;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
reg [9:0] ooutp;
wire [3:0] dataA;
wire [3:0] dataB;
reg [9:0] inner;
regfile y (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);
always #(posedge clk) begin
if (s0==0) begin
inner <= dataA [3:0]*dataB [3:0];
end
else begin
ooutp <= ((dataA [3:0]*dataB [3:0])+inner [9:0]);
end
end
endmodule
i write the verilog code which contain only adders. In this g,h are 10 bits and r5(main output) is of 11 bits. When i take r5 as 11 bits then i am not getting correct output but when i take r5 as 10 bits then i am getting correct. but (r5=g+h) so its bit should be one more than bits of g,h.
i took input as clk = 1;
s189 = 10'd200;
s375 = 10'd75;
s050 = 10'd300;
s218 = 10'd54;
and output should be r5= -16 but it gives output as (01111110000) instead of (11111110000)
module out(clk,s189,s375,s050,s218,r5,g,h);
input clk;
input [9:0] s189,s375,s050,s218;
output reg[10:0] r5;
output reg [9:0] g,h;
reg [3:0] countr=4'b0000;
always#(posedge clk)
begin
if (countr==4'b1000)
begin
g<= s218-s189;
h<= s375+s050;
r5<=g+h;
end
end
always#(posedge clk)
begin
if (countr==4'b1001)
countr<=4'b0000;
else
countr<= countr+1;
end
endmodule
You are performing unsigned arithmetic, as noted the MSB is 0 not 1 (negative) as expected. You need to declare the inputs, outputs and variables used as signed, for automatic sign extension.
module out(
input clk,
input signed [9:0] s189,
input signed [9:0] s375,
input signed [9:0] s050,
input signed [9:0] s218,
output reg signed [10:0] r5,
output reg signed [9:0] g,
output reg signed [9:0] h
);
I have a number of 32 bit. I need only its first 8 bits. I think I can do this by two methods: one is by shifting the number to 24 bits right and other is by simply assigning the last 8 bits to a variable.
Here is what I am trying to do:
module Data_shiftin(
input reset_n, clk,
input [31:0] data_in,
output [31:0] data_out
);
reg [31:0] data_reg;
reg data_out;
always # (posedge clk)
begin
data_out<=data_in[31:23];
end
endmodule
But I am getting only last bit i.e. 32nd bit of the number. I don't know where I am doing error.
Thanks!
P.S: I am a newbie to this language.
The assignment you have is correct, but you are only getting one bit because you are redeclaring data_out as a single-bit reg. Try changing:
reg data_out
To:
reg[31:0] data_out
A better option though it to use Verilog-2000 style port declarations and place the reg keyword in the port list.
Example:
module Data_shiftin(
input wire reset_n,
input wire clk,
input wire [31:0] data_in,
output reg [31:0] data_out
);
always # (posedge clk)
begin
data_out <= data_in[31:23];
end
endmodule
Note also that your tool may warn you about a width mismatch because you are assigning an 8-bit value to a 32-bit value. To explicitly assign only the lower 8 bits of data_out you should use:
data_out[7:0] <= data_in[31:23]