i write the verilog code which contain only adders. In this g,h are 10 bits and r5(main output) is of 11 bits. When i take r5 as 11 bits then i am not getting correct output but when i take r5 as 10 bits then i am getting correct. but (r5=g+h) so its bit should be one more than bits of g,h.
i took input as clk = 1;
s189 = 10'd200;
s375 = 10'd75;
s050 = 10'd300;
s218 = 10'd54;
and output should be r5= -16 but it gives output as (01111110000) instead of (11111110000)
module out(clk,s189,s375,s050,s218,r5,g,h);
input clk;
input [9:0] s189,s375,s050,s218;
output reg[10:0] r5;
output reg [9:0] g,h;
reg [3:0] countr=4'b0000;
always#(posedge clk)
begin
if (countr==4'b1000)
begin
g<= s218-s189;
h<= s375+s050;
r5<=g+h;
end
end
always#(posedge clk)
begin
if (countr==4'b1001)
countr<=4'b0000;
else
countr<= countr+1;
end
endmodule
You are performing unsigned arithmetic, as noted the MSB is 0 not 1 (negative) as expected. You need to declare the inputs, outputs and variables used as signed, for automatic sign extension.
module out(
input clk,
input signed [9:0] s189,
input signed [9:0] s375,
input signed [9:0] s050,
input signed [9:0] s218,
output reg signed [10:0] r5,
output reg signed [9:0] g,
output reg signed [9:0] h
);
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i tried to do it in two ways, and each time i got stuck by the same problem Error (10031): Net "copy_data_in[183]" at RotateText.sv(16) is already driven by input port "data_in[183]", and cannot be driven by another signal.
Hi , i have input of 23 elements that each one is 8 bits.i have output of 6 elements that each one is 8 bits.The input should get change each time. in the end it should be like circular printing. Excuse me but ENABLE should be CLK.
i tried to do it in two ways, and each time i got stuck by the same problem Error (10031): Net "copy_data_in[183]" at RotateText.sv(16) is already driven by input port "data_in[183]", and cannot be driven by another signal.
This first try :
module RotateText( data_in,HEX0S,HEX1S,HEX2S,HEX3S,HEX4S,HEX5S,ENABLE);
input [7:0] data_in [22:0];
input ENABLE;
output reg [7:0] HEX0S;
output reg [7:0] HEX1S;
output reg [7:0] HEX2S;
output reg [7:0] HEX3S;
output reg [7:0] HEX4S;
output reg [7:0] HEX5S;
reg [7:0] tmp;
reg [7:0] copy_data_in [22:0];
reg [7:0] tmp2;
integer i;
integer j=0;
always#(posedge ENABLE)begin
if(j==0)begin
for(i = 0; i < 23; i=i+1) begin
copy_data_in[i] <= data_in[i];
end
end
HEX5S<=copy_data_in[22];
HEX4S<=copy_data_in[21];
HEX3S<=copy_data_in[20];
HEX2S<=copy_data_in[19];
HEX1S<=copy_data_in[18];
HEX0S<=copy_data_in[17];
tmp<= copy_data_in[22];
copy_data_in[22:1]<=copy_data_in[21:0];
copy_data_in[0]<=tmp;
j=j+1;
end
endmodule
This is another approch :
module RotateText( data_in,HEX0S,HEX1S,HEX2S,HEX3S,HEX4S,HEX5S,ENABLE);
input [183:0] data_in ;
input ENABLE;
output reg [7:0] HEX0S;
output reg [7:0] HEX1S;
output reg [7:0] HEX2S;
output reg [7:0] HEX3S;
output reg [7:0] HEX4S;
output reg [7:0] HEX5S;
reg [7:0] tmp;
reg [183:0] copy_data_in;
integer i;
integer j=0;
integer index;
assign copy_data_in=data_in;
always#(posedge ENABLE)begin
HEX5S<=copy_data_in[183:176];
HEX4S<=copy_data_in[175:168];
HEX3S<=copy_data_in[167:160];
HEX2S<=copy_data_in[159:152];
HEX1S<=copy_data_in[151:144];
HEX0S<=copy_data_in[143:136];
tmp<=data_in[183:176];
copy_data_in<=copy_data_in<<8;
copy_data_in[7:0]<=tmp;
end
endmodule
glad to get help .
The post has a circular shift register (sr).
An sr accepts input from the previous stage or from a module input for loading; not both at the same time. Loading & shifting are mutually exclusive behaviors in the same clock clock cycle. The design needs a input control signal to decide load or shift.
The posted code errors out, because its trying to drive the sr internally, and from inputs at the same time.
Here is a solution based on the posted code.
Variable load_shiftn determines load or shift .
module rot(
input logic clk,
input [7:0] data_in [22:0],
input logic load_shiftn,
output reg [7:0] HEX0S,
output reg [7:0] HEX1S,
output reg [7:0] HEX2S,
output reg [7:0] HEX3S,
output reg [7:0] HEX4S,
output reg [7:0] HEX5S
);
// internal
reg [7:0] sr [22:0];
always#(posedge clk)begin
if(load_shiftn)
sr <= data_in;
else begin
sr[22:1] <= sr[21:0];
sr[0] <= sr[22];
end
end
always # * begin
HEX5S =sr[22];
HEX4S =sr[21];
HEX3S =sr[20];
HEX2S =sr[19];
HEX1S =sr[18];
HEX0S =sr[17];
end
endmodule
Testbench
module tb ();
bit clk;
logic [7:0] data_in [22:0];
bit load_shiftn;
logic [7:0] HEX0S;
logic [7:0] HEX1S;
logic [7:0] HEX2S;
logic [7:0] HEX3S;
logic [7:0] HEX4S;
logic [7:0] HEX5S;
always #5 clk = !clk;
initial begin
#270;
$finish;
end
rot u1 (.*);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
initial begin
foreach(data_in[i])
data_in[i] = i;
end
initial begin
#(posedge clk)
load_shiftn <= 1;
repeat(2) #(posedge clk);
load_shiftn <= 0;
end
endmodule
Waves
I'm Trying to make a 64-bit shift register in Verilog HDL. When I try the code in the testbench, I just get xxxxxx as the output till all the bits have been shifted. I don't know what the problem is.
Here Is my code with the testbench and the result:
module ShiftRegister (shift_out, clk, shift_in); //module ports
parameter n = 64; //Parameter n declared to store 64
input [n-1:0] shift_in; //64-bit input shift_in
input clk; //Input clock
output [n-1:0] shift_out; //64-bit output shift_out
reg [n-1:0] ff; //64-bit flipflop
assign shift_out = ff [n-1:0]; //give the output of the 64th bit
//The operation of verilog:
always # (posedge clk) //Always at the rising edge of the clock
begin
ff <= ff << 1; //Shift bits to the left by 1
ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
end
endmodule //ShiftRegister module
///Testbench\\\
module ShiftRegister_tb; //Module shiftRegister_tb
parameter n = 64; //Parameter n declared to store 64
reg [n-1:0] shift_in; //64-bit register input shift_in
reg clk, rst; //register clock
wire [n-1:0] shift_out; //64-bit wire output shift_out
ShiftRegister DUT(shift_out, clk, shift_in); //Calling the module
initial
begin
clk = 0; //clock = 0 initally
shift_in = 64'd34645767785344; //Random decimal number to test the code
#100;
end
always #50 clk =~clk; //invert the clock input after 50ps
endmodule //ShiftRegister testbench
You declare ff as a reg, and the default value of a reg is x. Before the 1st posedge of the clock, all 64 bits of ff are x (unknown). After the 1st posedge of the clock, ff[0] becomes 0 because shift_in[0] is 0. And so on, until you reach 64 clocks, then all ff bits are 0. shift_out just follows ff.
Typically, your design would also have a reset signal. If you had one, you could assert reset at the start, and assign ff to 0 during reset. Here is what is looks like with a reset:
module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
parameter n = 64; //Parameter n declared to store 64
input rst;
input [n-1:0] shift_in; //64-bit input shift_in
input clk; //Input clock
output [n-1:0] shift_out; //64-bit output shift_out
reg [n-1:0] ff; //64-bit flipflop
assign shift_out = ff [n-1:0]; //give the output of the 64th bit
always # (posedge clk or posedge rst) //Always at the rising edge of the clock
begin
if (rst) begin
ff <= 0;
end else begin
ff <= ff << 1; //Shift bits to the left by 1
ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
end
end
endmodule
module ShiftRegister_tb; //Module shiftRegister_tb
parameter n = 64; //Parameter n declared to store 64
reg [n-1:0] shift_in; //64-bit register input shift_in
reg clk, rst; //register clock
wire [n-1:0] shift_out; //64-bit wire output shift_out
ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
initial
begin
clk = 0; //clock = 0 initally
rst = 1;
shift_in = 64'd34645767785344; //Random decimal number to test the code
#100;
rst = 0;
#50_000 $finish;
end
always #50 clk =~clk; //invert the clock input after 50ps
endmodule
module tb_alu32();
reg clk, reset;
reg [31:0] tb_a, tb_b, tb_yexpected;
reg [2:0] tb_op;
wire [31:0] tb_result;
reg[31:0] vectornum, errors;
reg[99:0] testvectors[10000:0];
...
always
begin
clk=0;#5;clk=1;#5;
end
$readmemh("C:/altera/13.0/practice/week3/alu32/testvect.tv",testvectors);
always # (posedge clk)
begin
#1; {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];
end
endmodule
I read testvect.tv but tb_a and tb_b's MSB are missing and LSB is set 0 like
0000_0001->0000_0002
0000_0002->0000_0004
FFFF_FFFF->FFFF_FFFE
FFFF_FFFE->FFFF_FFFC
8000_0001->0000_0002
How can I solve this?
If I use readmemb, it works well.
If I assign values it works well.
Why did it happen?
This is what is causing the error
Your {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];
LHS is 99 bits and RHS is 100 bits. Just declare
reg[98:0] testvectors[10000:0];
i.e instead of 100 bits, declare testvectors to be 99 bits.
I just started to work with CRC32.So when I wanted to check the code I wrote and I get xxxxxx as the output.I am not sure if the code is right though
module last_time(input [127:0]finalinput,output [31:0]crcout1
,input clk);
wire [31:0]poly;
assign poly=32'h04c11db7;
reg [7:0]lsb;
reg [3:0]i;
reg [7:0]ans;
reg [31:0]nextcrc;
reg [31:0]newcrc;
reg [31:0]crcout;
reg [7:0] lut [255:0];
always#(posedge clk)
begin
crcout=32'hffffffff;
lsb=finalinput;
for(i=0;i<16;i=i+1)
begin
ans=(8'hff^(lsb));
newcrc = lut[ans];
$readmemh("table.txt",lut); // to fill lut
nextcrc=(newcrc)^(crcout>>8);
lsb=lsb>>8;
end
end
assign crcout1=nextcrc^32'hffffffff;
endmodule
The issue was with the input to the LUT, it should be an integer and not a reg value.
The LUT size was not the correct size
module bit32(input [31:0]msg,input [31:0]crcinitial,output reg[31:0]tableout,output [23:0]crcshifted,
output[31:0]newcrc,output reg [7:0]xor1);
wire [7:0]msglsb;
assign msglsb=msg;
wire [7:0]crclsb;
assign crclsb=crcinitial;
integer k;
reg [31:0]lut[0:255];
initial
begin
assign xor1=(crclsb^msglsb)&8'hff;
assign k=xor1;
assign tableout=lut[xor1];
$readmemh("table.txt",lut);
end
assign crcshifted=crcinitial>>8;
assign newcrc=(tableout^crcshifted)^32'hffffffff;
endmodule
I have a number of 32 bit. I need only its first 8 bits. I think I can do this by two methods: one is by shifting the number to 24 bits right and other is by simply assigning the last 8 bits to a variable.
Here is what I am trying to do:
module Data_shiftin(
input reset_n, clk,
input [31:0] data_in,
output [31:0] data_out
);
reg [31:0] data_reg;
reg data_out;
always # (posedge clk)
begin
data_out<=data_in[31:23];
end
endmodule
But I am getting only last bit i.e. 32nd bit of the number. I don't know where I am doing error.
Thanks!
P.S: I am a newbie to this language.
The assignment you have is correct, but you are only getting one bit because you are redeclaring data_out as a single-bit reg. Try changing:
reg data_out
To:
reg[31:0] data_out
A better option though it to use Verilog-2000 style port declarations and place the reg keyword in the port list.
Example:
module Data_shiftin(
input wire reset_n,
input wire clk,
input wire [31:0] data_in,
output reg [31:0] data_out
);
always # (posedge clk)
begin
data_out <= data_in[31:23];
end
endmodule
Note also that your tool may warn you about a width mismatch because you are assigning an 8-bit value to a 32-bit value. To explicitly assign only the lower 8 bits of data_out you should use:
data_out[7:0] <= data_in[31:23]