I need to program a sequential circuit in Verilog code as a pattern generator which generates, instead of binary counts, your Firstname (space) Lastname (space), character by character. I need to display the pattern sequence for at least two cycles.
diagram
This is the sample output:
sampleoutput
I know that the issue my program has is in the CoderMod module, but I'm not sure where the issues are.
Thanks for the help!
//pattern.v
module TestMod;
reg CLK;
wire [0:11] Q;
wire [6:0] ascii;
initial begin
#1;
forever begin
CLK=0;
#1;
CLK=1;
#1;
end
end
RippleMod my_ripple(CLK, Q);
CoderMod my_coder(Q, ascii);
initial #27 $finish;
initial begin
$display("Time CLK Q Name");
$monitor("%4d %b %b %c %x %b", $time, CLK, Q, ascii, ascii, ascii);
end
endmodule
module CoderMod(Q, ascii);
input [0:13]Q;
output [13:0] ascii;
assign ascii[0] = "F";
assign ascii[1] = "i";
assign ascii[2] = "r";
assign ascii[3] = "s";
assign ascii[4] = "t";
assign ascii[5] = " ";
assign ascii[6] = "L";
assign ascii[7] = "a";
assign ascii[8] = "s";
assign ascii[9] = "t";
assign ascii[10] = "n";
assign ascii[11] = "a";
assign ascii[12] = "m";
assign ascii[13] = "e";
or(ascii[0], Q[13]);
or(ascii[1], Q[12]);
or(ascii[2], Q[11]);
or(ascii[3], Q[10]);
or(ascii[4], Q[9]);
or(ascii[5], Q[8]);
or(ascii[6], Q[7]);
or(ascii[7], Q[6]);
or(ascii[8], Q[5]);
or(ascii[9], Q[4]);
or(ascii[10], Q[3]);
or(ascii[11], Q[2]);
or(ascii[12], Q[1]);
or(ascii[13], Q[0]);
endmodule
module RippleMod(CLK, Q);
input CLK;
output [0:15]Q;
reg [0:15]Q;
always #(posedge CLK) begin
Q[0] <= Q[15];
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
Q[4] <= Q[3];
Q[5] <= Q[4];
Q[6] <= Q[5];
Q[7] <= Q[6];
Q[8] <= Q[7];
Q[9] <= Q[8];
Q[10] <= Q[9];
Q[11] <= Q[10];
Q[12] <= Q[11];
Q[13] <= Q[12];
Q[14] <= Q[13];
Q[15] <= Q[14];
end
initial begin
Q[0] = 1;
Q[1] = 0;
Q[2] = 0;
Q[3] = 0;
Q[4] = 0;
Q[5] = 0;
Q[6] = 0;
Q[7] = 0;
Q[8] = 0;
Q[9] = 0;
Q[10] = 0;
Q[11] = 0;
Q[12] = 0;
Q[13] = 0;
Q[14] = 0;
Q[15] = 0;
end
endmodule
There are actually multiple issues with your program. i.e. you declare an ascii arraya as wire [6:0] ascii; but later you connect it to the module as CoderMod my_coder(Q, ascii); where it is an output port of width 14. You also assig 8-bit characters to a one-bit ascii, like here: ascii[1] = "i";
as a hint, you need to declare it as
wire [6:0] ascii [13:0];
you shold be able to figure out the rest.
Related
The below code is for a FIFO. It is showing an error as illegal reference to net datatype as rddata at line 38 in tb (highlighted by adding a comment "//error line").
Why do I get this error?
module fifo(clk,rst,error,empty,full,rddata,wrdata,wr_en,rd_en);
parameter WIDTH = 8;
parameter DEPTH = 16;
input clk,rst,rd_en,wr_en;
input [WIDTH-1:0]wrdata;
output reg [WIDTH-1:0]rddata;
output reg empty,full,error;
reg [WIDTH-1:0]mem[DEPTH-1:0];
reg [3:0]rd_ptr;
reg [3:0]wr_ptr;
reg wr_toggle,rd_toggle;
integer i;
always#(posedge clk)
begin
if(rst==1)
begin
empty = 1;
full = 0;
error = 0;
rd_ptr = 0;
wr_ptr = 0;
wr_toggle = 0;
rd_toggle = 0;
for(i=1;i<DEPTH;i=i+1)
begin
mem[i] = 0;
end
end
else
begin
if(wr_en ==1)begin
if(full==1)begin
$display("ERROR:Writing to full FIFO");
error = 1;
end
else
begin
mem[wr_ptr] = wrdata;
if(wr_ptr == DEPTH-1)begin
wr_toggle = ~wr_toggle;
wr_ptr = 0;
end
else begin
wr_ptr = wr_ptr + 1;
end
end
end
if(rd_en ==1)begin
if(empty==1)begin
$display("ERROR:REading from EMPTY FIFO");
error = 1;
end
end
else
begin
mem[rd_ptr] = rddata;
if(rd_ptr == DEPTH-1)begin
rd_toggle = ~rd_toggle;
rd_ptr = 0;
end
else begin
rd_ptr = rd_ptr + 1;
end
end
end
end
always#(wr_ptr or rd_ptr)
begin
full = 0;
empty = 0;
if(wr_ptr == rd_ptr && wr_toggle == rd_toggle)begin
empty = 1;
full = 0;
end
if(wr_ptr == rd_ptr && wr_toggle != rd_toggle)begin
empty = 0;
full = 1;
end
end
endmodule
//TEST BENCH
`include "fifo.v"
module tbfifo();
parameter WIDTH = 8;
parameter DEPTH = 16;
reg clk,rst,rd_en,wr_en;
reg [WIDTH-1:0]wrdata;
wire [WIDTH-1:0]rddata;
wire empty,full,error;
integer i;
fifo_buff dut (clk,rst,error,empty,full,rddata,wrdata,wr_en,rd_en);
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
rst = 1;
repeat(2) #(posedge clk);
rst = 0;
for(i=0;i<DEPTH;i=i+1)begin
#(posedge clk);
wr_en = 1;
wrdata = $random;
end
#(posedge clk);
wr_en = 0;
wrdata= 0;
for(i=0;i<DEPTH;i=i+1)begin
#(posedge clk);
rd_en = 1;
rddata <= $random; //error line
end
#(posedge clk);
rd_en = 0;
#100;
$finish;
end
endmodule
rddata is an output port of the fifo_buff module. In the testbench, there is a wire named rddata which connects to the fifo instance.
The problem is that the testbench then tries to drive the signal:
rddata <= $random; //error line
That is illegal. You can not make a procedural assignment (inside an initial block, for example) to a wire. And, you should not try to drive that signal from the testbench since it is already driven by the module instance, because that would results in multiple drivers (contention). You must remove this line.
for (i=0; i<DEPTH; i=i+1) begin
#(posedge clk);
rd_en = 1;
end
#(posedge clk);
rd_en = 0;
Typically, you would monitor an output signal in the testbench (display its value or compare it against a reference model). This is usually done in a separate process (always block, for example) from the input driving process.
I'm trying to make MIPS Data Memory with Verilog.
The code does not work properly. It is unable to read and write as of right now. I thought the code that I made is correct, but if there is any flaw in here, please make it work. The code below is what I made and used.
//WORD_LEN = 32
//MEM_CELL_SIZE = 8
//DATA_MEM_SIZE = 1024
module DataMemory(CLK, rst, Addr, WriteData, ReadData, MemRead, MemWrite);
input CLK, rst;
input MemRead, MemWrite; //switch
input [`WORD_LEN-1:0] Addr, WriteData;
output reg[`WORD_LEN-1:0] ReadData;
reg [`MEM_CELL_SIZE-1:0] DataMem [0:`DATA_MEM_SIZE];
wire [`WORD_LEN-1:0] Pointer;
integer i;
always #(negedge CLK) //Write on memory needs CLK
begin
if(rst)
for (i = 0; i < `DATA_MEM_SIZE; i = i + 1)
DataMem[i] <= 0;
/*
// Identify each DataMem
*/
else if(MemWrite == 1 && MemRead == 0) // Store Word
{DataMem[Pointer], DataMem[Pointer+1], DataMem[Pointer+2], DataMem[Pointer+3]} <= WriteData;
else if(MemWrite == 0 && MemRead == 1) // Load Word
ReadData <= ((Addr >= 1024) ? 0 : {DataMem[Pointer], DataMem[Pointer+1], DataMem[Pointer+2], DataMem[Pointer+3]});
end
// Pointer must be added 4 shifter >>2 << 2 helps to flush 1~3
assign Pointer = (Addr >> 2) << 2;
endmodule
And Testbench which I use below here.
`include "Defines.v"
//WORD_LEN = 32
//MEM_CELL_SIZE = 8
//DATA_MEM_SIZE = 1024
module DataMemoryTest;
reg CLK, rst;
reg MemRead, MemWrite;
reg [`WORD_LEN-1:0] Addr, WriteData;
wire [`WORD_LEN-1:0]ReadData;
DataMemory TestDataMemory(.CLK(CLK), .rst(rst), .Addr(Addr), .WriteData(WriteData),
.ReadData(ReadData), .MemRead(MemRead), .MemWrite(MemWrite));
initial begin
CLK = 1;
repeat(5000) #50 CLK = ~CLK;
end
initial begin
rst = 1;
#100;
MemRead = 0;
MemWrite = 1;
Addr = 32'd0;
WriteData = 32'd123;
#100;
MemRead = 0;
MemWrite = 1;
Addr = 32'd4;
WriteData = 0;
#100;
MemRead = 0;
MemWrite = 1;
Addr = 32'd8;
WriteData = 32'd17;
#100;
MemRead = 1;
MemWrite = 0;
Addr = 32'd12;
WriteData = 32'd123;
#100;
MemRead = 1;
MemWrite = 0;
Addr = 32'd16;
WriteData = 0;
#100;
MemRead = 1;
MemWrite = 0;
Addr = 32'd20;
WriteData = 32'd17;
end
endmodule
The testbench keeps the design in reset. You need to set rst=0 after some delay.
initial begin
rst = 1;
#500;
rst = 0;
#100;
MemRead = 0;
MemWrite = 1;
Addr = 32'd0;
WriteData = 32'd123;
I can't figure out , where this errors.Invalid use of input signal <ck> as target error is coming from?
module register
#(parameter Width = 8)
(output reg [Width-1:0] out,
input [Width-1:0] in,
input clear, load, clock);
always #(posedge clock)
if (~clear)
out<= 0;
else if (~load)
out<=in;
endmodule
module adder
#(parameter Width = 8)
(input [Width-1:0] a,b,
output [Width-1:0] sum);
assign sum = a + b;
endmodule
module compareLT // compares a < b
#(parameter Width = 8)
(input [Width-1:0] a, b,
output out);
assign out = a < b;
endmodule
module compareLEQ // compares a <= b
#(parameter Width = 8)
(input [Width-1:0] a, b,
output out);
assign out = a <= b;
endmodule
module roshanpoop
#(parameter Width = 8)
(input ck, reset,
input [Width-1:0] yln,
output [Width-1:0] y, x);
wire [Width-1:0] i, addiOut, addxOut;
wire yLoad, yClear, xLoad, xClear, iLoad,iClear;
register #(Width) I (i, addiOut, iClear, iLoad, ck);
register #(Width) Y (y, yIn, yClear, yLoad, ck);
register #(Width) X (x, addxOut, xClear, xLoad, ck);
adder #(Width) addI (addiOut, 'b1, i),
addX (x, y, addxOut);
compareLT #(Width) cmpX (x, 'b0, xLT0);
compareLEQ #(Width) cmpI (i, 'd10, iLEQ10);
fsm ctl (xLT0,iLEQ10 ,yLoad, yClear, xLoad, xClear, iLoad,iClear, ck, reset);
endmodule
module fsm
(input LT,LEQ, ck, reset,
output reg yLoad, yClear, xLoad, xClear, iLoad, iClear);
reg [2:0] cState, nState;
always #(posedge ck,negedge reset)
if (~reset)
cState <= 0;
else
cState <= nState;
always#(cState, LT,LEQ)
case (cState)
3'b00: begin //stateA
yLoad = 1; yClear = 1; xLoad = 1; xClear = 0;
iLoad = 1; iClear = 0; nState = 3'b001;
end
3'b001: begin // state B
yLoad = 1; yClear = 1; xLoad = 0; xClear = 1;
iLoad = 0; iClear = 1; nState = 3'b010;
end
3'b010: begin //state C
yLoad = 1; yClear = 1; xLoad = 1; xClear = 1;
iLoad = 1; iClear = 1;
if(LEQ) nState = 3'b001;
if(~LEQ & LT) nState = 3'b011;
if (~LEQ & ~LT) nState = 3'b100;
end
3'b011: begin //state D
yLoad = 1; yClear = 0; xLoad = 1; xClear = 1;
iLoad = 1; iClear = 1; nState = 3'b101;
end
3'b100: begin //state E
yLoad = 1; yClear = 1; xLoad = 1; xClear = 0;
iLoad = 1; iClear = 1; nState = 3'b101;
end
default: begin // required to satisfy combinational synthesis rules
yLoad = 1; yClear = 1; xLoad = 1; xClear = 1;
iLoad = 1; iClear = 1;nState = 3'b000;
$display("Oops, unknown state: %b", cState);
end
endcase
endmodule
error:
line no:70
Invalid use of input signal ck as target,
Invalid use of input signal target as target.
In module roshanpoop above mentioned error are coming . what might be the problem ?
The error is caused by this instantiation:
fsm ctl (xLT0,iLEQ10 ,yLoad, yClear, xLoad, xClear, iLoad,iClear, ck, reset);
of the module:
module fsm
(input LT,LEQ, ck, reset,
output reg yLoad, yClear, xLoad, xClear, iLoad, iClear);
You are using positional instantiation, which is not recomended, because it makes the task of maintaining your module more difficult (think, for example, if you want to add signals to your module: if you add it in the middle of the module's definition, all remaining signals will be wrongly connected).
Here, the use of positional instantiation has caused signal ck from the top module to be connected to iLoad, which is an output signal from fsm, so you are trying to put a value to a input only signal ck.
The way to have it right is to use explicit instantiation, where each signal from the module is explicitly named and assigned to a signal from the top module, like this:
fsm ctl (.LT(xLT0),
.LEQ(iLEQ10),
.yLoad(yLoad),
.yClear(yClear),
.xLoad(xLoad),
.xClear(xClear),
.iLoad(iLoad),
.iClear(iClear),
.ck(ck),
.reset(reset)
);
So, regardless of where in the argument list you put signal clk it will be always connected to the right signal inside the module.
Not an answer but some tips on potentially making the code easier to understand. I would post as a comment but code examples do not work well in comments.
1) Manual sensitivity lists can [should] be avoided when using a modern toolset.
always#(cState, LT,LEQ)
With an automatic sensitivity list would just be:
always #(*)
// Or
always #*
If you are able to use SystemVerilog (as question tags indicate) then the preferred method is :
always_comb
2) Instead of:
yLoad = 1; yClear = 1; xLoad = 1; xClear = 0;
iLoad = 1; iClear = 0;
For every case, we could have
reg [5:0] temp_control;
assign {yLoad, yClear xLoad, xClear, iLoad, iClear} = temp_control;
//...
always #*
case(cState)
3'b000: begin //stateA
temp_control = 6'b111010; nState = 3'b001;
end
3'b001: begin // state B
temp_control = 6'b110101; nState = 3'b010;
end
3'b010: begin //state C
temp_control = 6'b111111;
if(LEQ) nState = 3'b001;
if(~LEQ & LT) nState = 3'b011;
if (~LEQ & ~LT) nState = 3'b100;
end
//...
Better still create Mnemonics for the temp_controls.
localparam [5:0] CTRL_LOAD = 6'b111010;
localparam [5:0] CTRL_CLEAR = 6'b111010;
Mnemonics for the states are also really helpful:
localparam [2:0] STATE_INIT = 3'b000;
localparam [2:0] STATE_START = 3'b001;
localparam [2:0] STATE_STOP = 3'b010;
The the FSM structure might look some thing like:
always #*
case(cState)
STATE_INIT: begin //stateA
temp_control = CTRL_LOAD; nState = STATE_START;
end
STATE_START: begin // state B
temp_control = CTRL_CLEAR; nState = STATE_STOP;
end
STATE_STOP: begin //state C
temp_control = CTRL_HALT;
if(LEQ) nState = STATE_START;
if(~LEQ & LT) nState = STATE_RECYCLE;
if (~LEQ & ~LT) nState = STATE_CRUSH;
end
As the readability improves it is often easier to spot an incorrectly used signal.
I have a homework problem where I'm supposed to create a module for single-precision IEEE-754 floating point multiplication. This is the module:
module prob3(a, b, s);
input [31:0] a, b; // operands
output reg [31:0] s; // sum - Could potentially use wire instead
integer i; // loop variable
reg [8:0] temp;
reg [47:0] intProd; // intermediate product
reg [23:0] tempA;
reg [23:0] tempB;
initial begin
//Initialization
for (i = 0; i < 48; i = i + 1) begin
intProd[i] = 0;
end
//Compute the sign for the result
if (a[31]^b[31] == 0) begin
s[31] = 0;
end
else begin
s[31] = 1;
end
//Compute the exponent for the result
#10 temp = a[30:23] + b[30:23] - 8'b11111111;
//Case for overflow
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
//Case for underflow
else if (temp < 8'b00000001) begin
for (i = 0; i < 31; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else begin
s[30:23] = temp[7:0];
end
//Mutliply the signficands
//Make implicit one explicit
tempA[23] = 1;
tempB[23] = 1;
//Make operands 24 bits
for(i = 0; i < 23; i = i + 1) begin
tempA[i] = a[i];
tempB[i] = b[i];
end
//Compute product of signficands
intProd = tempA * tempB;
//Check and see if we need to normalize
if(intProd[47:46] >= 2'b10) begin
intProd = intProd >> 1;
temp = s[30:23] + 1'b1;
if(temp > 8'b11111110) begin
s[30:23] = 8'b11111111;
for (i = 0; i < 23; i = i + 1) begin
s[i] = 0;
end
$finish;
end
else
s[30:23] = temp[7:0];
end
s[22:0] = intProd[47:25];
end
endmodule
Here is my testbench:
module prob4;
reg [31:0] a, b;
wire [31:0] s;
// instantiate the floating point multiplier
prob3 f1(a, b, s);
initial begin
assign a = 32'h42055555;
assign b = 32'hBDCCCCCD;
#10 $monitor("s = %h", s);
assign a = 32'hBF555555;
assign b = 32'hCAB71B00;
#10 $monitor("s = %h", s);
a = 32'hFF500000;
b = 32'h7E700000;
#10 $display("s = %b", s);
a = 32'h01700000;
b = 32'h02F00000;
#10 $display("s = %b", s);
a = 32'hBE000000;
b = 32'h455F36DB;
#10 $display("s = %b", s);
a = 32'h3C800000;
b = 32'h3A800000;
#10 $display("s = %b", s);
a = 32'hC797E880;
b = 32'hB7FBA927;
#10 $display("s = %b", s);
end
endmodule
It displays the first value of s, but that is it. I'm honestly not too familiar with Verilog, so any clarification on why this might be happening would be truly appreciated.
The reason you are seeing only a single value for s is because all of your floating point logic (all the stuff in the prob3 module) is inside an initial block. Thus, you only run that code once; it starts at time 0, has a pause for 10 time units and finishes; never to run again. Here are a few tips for implementing the unit (assuming the module is suppose to be synthesizable and not just a functional verification model):
Place your combinational logic in an always #(*) block, not an initial block.
As toolic mentioned, only call $monitor once, and it will inform you whenever s or any other variables given as arguments change; thus you do not need the $display statements either unless you want to know the value of s at that point of execution (whether it changed or not and inline with the processes, so not necessarily the final value either). So typically your testbench main stimulus initial block would have $monitor() as the first line.
Don't call $finish inside your logic; ideally, you should set an error signal instead that the testbench might then choose to call $finish if it sees that error signal asserted.
Don't use assign inside procedural blocks (always, initial, etc), just say a = ... not assign a = ...
I am trying to reduce a vector to a sum of all it elements. Is there an easy way to do this in verilog?
Similar to the systemverilog .sum method.
Thanks
My combinational solution for this problem:
//example array
parameter cells = 8;
reg [7:0]array[cells-1:0] = {1,2,3,4,5,1,1,1};
//###############################################
genvar i;
wire [7:0] summation_steps [cells-2 : 0];//container for all sumation steps
generate
assign summation_steps[0] = array[0] + array[1];//for less cost starts witch first sum (not array[0])
for(i=0; i<cells-2; i=i+1) begin
assign summation_steps[i+1] = summation_steps[i] + array[i+2];
end
endgenerate
wire [7:0] result;
assign result = summation_steps[cells-2];
Verilog doesn't have any built-in array methods like SV. Therefore, a for-loop can be used to perform the desired functionality. Example:
parameter N = 64;
integer i;
reg [7:0] array [0:N-1]
reg [N+6:0] sum; // enough bits to handle overflow
always #*
begin
sum = {(N+7){1'b0}}; // all zero
for(i = 0; i < N; i=i+1)
sum = sum + array[i];
end
In critiquing the other answers delivered here, there are some comments to make.
The first important thing is to provide space for the sum to be accumulated. statements such as the following, in RTL, won't do that:
sum = sum + array[i]
because each of the unique nets created on the Right Hand Side (RHS) of the expression are all being assigned back to the same signal called "sum", leading to ambiguity in which of the unique nets is actually the driver (called a multiple driver hazard). To compound the problem, this statement also creates a combinational loop issue because sum is used combinationally to drive itself - not good. What would be good would be if something different could be used as the load and as the driver on each successive iteration of the loop....
Back to the argument though, in the above situation, the signal will be driven to an unknown value by most simulator tools (because: which driver should it pick? so assume none of them are right, or all of them are right - unknown!!). That is if it manages to get through the compiler at all (which is unlikely, and it doesn't at least in Cadence IEV).
The right way to do it would be to set up the following. Say you were summing bytes:
parameter NUM_BYTES = 4;
reg [7:0] array_of_bytes [NUM_BYTES-1:0];
reg [8+$clog2(NUM_BYTES):0] sum [NUM_BYTES-1:1];
always #* begin
for (int i=1; i<NUM_BYTES; i+=1) begin
if (i == 1) begin
sum[i] = array_of_bytes[i] + array_of_bytes[i-1];
end
else begin
sum[i] = sum[i-1] + array_of_bytes[i];
end
end
end
// The accumulated value is indexed at sum[NUM_BYTES-1]
Here is a module that works for arbitrarily sized arrays and does not require extra storage:
module arrsum(input clk,
input rst,
input go,
output reg [7:0] cnt,
input wire [7:0] buf_,
input wire [7:0] n,
output reg [7:0] sum);
always #(posedge clk, posedge rst) begin
if (rst) begin
cnt <= 0;
sum <= 0;
end else begin
if (cnt == 0) begin
if (go == 1) begin
cnt <= n;
sum <= 0;
end
end else begin
cnt <= cnt - 1;
sum <= sum + buf_;
end
end
end
endmodule
module arrsum_tb();
localparam N = 6;
reg clk = 0, rst = 0, go = 0;
wire [7:0] cnt;
reg [7:0] buf_, n;
wire [7:0] sum;
reg [7:0] arr[9:0];
integer i;
arrsum dut(clk, rst, go, cnt, buf_, n, sum);
initial begin
$display("time clk rst sum cnt");
$monitor("%4g %b %b %d %d",
$time, clk, rst, sum, cnt);
arr[0] = 5;
arr[1] = 6;
arr[2] = 7;
arr[3] = 10;
arr[4] = 2;
arr[5] = 2;
#5 clk = !clk;
#5 rst = 1;
#5 rst = 0;
#5 clk = !clk;
go = 1;
n = N;
#5 clk = !clk;
#5 clk = !clk;
for (i = 0; i < N; i++) begin
buf_ = arr[i];
#5 clk = !clk;
#5 clk = !clk;
go = 0;
end
#5 clk = !clk;
$finish;
end
endmodule
I designed it for 8-bit numbers but it can easily be adapted for other kinds of numbers too.