I have a Verilog program where I have to model an ALU that can add, subtract, check for equality and divide by 2. My code:
module alu(
input wire [7:0] sw,
output reg [2:0] s,
output reg cout
);
reg co1, co2;
always #(*) begin
if(~sw[6] & ~sw[7]) begin
s[0] = sw[0] ^ sw[3] ^ 1'b0;
co1 = (sw[3] & 1'b0) | (sw[0] & 1'b0) | (sw[0] & sw[3]);
s[1] = sw[1] ^ sw[4] ^ co1;
co2 = (sw[4] & co1) | (sw[1] & co1) | (sw[1] & sw[4]);
s[2] = sw[2] ^ sw[5] ^ co2;
cout = (sw[5] & co2) | (sw[2] & co2) | (sw[2] & sw[5]);
end
else if(sw[6] & ~sw[7]) begin
s[0] = sw[0] ^ ~sw[3] ^ 1'b1;
co1 = (~sw[3] & 1'b1) | (sw[0] & 1'b1) | (sw[0] & ~sw[3]);
s[1] = sw[1] ^ ~sw[4] ^ co1;
co2 = (~sw[4] & co1) | (sw[1] & co1) | (sw[1] & ~sw[4]);
s[2] = sw[2] ^ ~sw[5] ^ co2;
cout = (~sw[5] & co2) | (sw[2] & co2) | (sw[2] & ~sw[5]);
end
\\more code
end
endmodule
I am getting this warning for 'co1' and 'co2'
signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
I am confused with the warning because from my understanding 'co1' and 'co2' are used to assign something. Overall when I run it on my board I get no outputs at all.
So this ended up being a non-issue. They were removed after synthesis.
Related
I was trying to write Verilog code of a two bit comparator, but I keep getting errors. Any help?
Error Codes:
10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(5) near text: ";"; expecting ")"
10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(7) near text: ";"; expecting ")"
10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(15) near text: "~"; expecting ")"
Design:
module twobit_comparator(
//assigning inputs
input wire [1:0] A, B;
// assigning outputs
output wire LT, GT, EQ;
// L=Less, G=Greater, E=Equal
);
wire [9:0] s;
//A = B output
assign s0 = (~A[1] & ~A[0] & ~B[1] ~B[0]);
assign s1 = (~A[1] & A[0] & ~B[1] & B[0]);
assign s2 = (A[1] & ~A[0] & B[1] & ~B[0]);
assign s3 = (A[1] & A[0] & b[1] & B[0]);
assign EQ = s0 | s1 | s2 | s3;
//A less than B output
assign s4 = (~A[0]) & (~A[1]) & B[0];
assign s5 = (~A[1]) & B[1];
assign s6 = (~A[0]) & B[1] & B[0];
assign LT = s4 | s5| s6;
// A greater than B output
assign s7 = (~B[0]) & (~B[1]) & A[0];
assign s8 = (~B[1]) & A[1];
assign s9 = (~B[0]) & A[1] & A[0];
assign GT = s7 | s8 | s9;
endmodule
Separate ports with commas, not semicolons, and do not end the port list with a semicolon:
module twobit_comparator(
//assigning inputs
input wire [1:0] A, B,
// assigning outputs
output wire LT, GT, EQ
// L=Less, G=Greater, E=Equal
);
You are missing the & operator; I added it here:
assign s0 = (~A[1] & ~A[0] & ~B[1] & ~B[0]);
// ^
I changed b to B here (Verilog is case-sensitive):
assign s3 = (A[1] & A[0] & B[1] & B[0]);
// ^
I don't get any more compile errors with the changes above. However, you declared signal s, but it is not used. And, you did not declare s0, s1, etc., but you are using them. This works because Verilog allows you to use undeclared wires when they are 1-bit wide. But, you should declare all signals. For example, you could use:
wire [9:0] s;
assign s[0] = (~A[1] & ~A[0] & ~B[1] & ~B[0]);
assign s[1] = (~A[1] & A[0] & ~B[1] & B[0]);
module seg_controller(
clk,
reset,
sel,
seg,);
input clk;
input reset;
output wire [5:0] sel;
output wire [7:0] seg;
wire [9:0] count;
wire [3:0] d_in;
counter use_counter(clk, reset, count);
FSM(count, reset, sel, d_in);
dec_7seg(d_in,seg);
endmodule
At this part, I don't know how to connect modules each others.
Each modules have many variables, but except input clk, reset how should i use variables in count, d_in.
just use wire?
module counter
(clk,
reset,
count);
input clk;
input reset;
output reg [9:0] count;
always # (posedge clk)
begin
if(reset) count <= 0;
else count <= count + 1;
end
endmodule
module FSM (
count,
reset,
sel,
d_in);
input [9:0]count;
input reset;
output reg [5:0] sel;
output reg [3:0] d_in;
reg [5:0] state, nextstate;
parameter S0 = 6'b100_000;
parameter S1 = 6'b010_000;
parameter S2 = 6'b001_000;
parameter S3 = 6'b000_100;
parameter S4 = 6'b000_010;
parameter S5 = 6'b000_001;
always # (*)
begin
if(reset) sel = 6'b100_000;
else if(count == 10'b11_1111_1111)
state = nextstate;
d_in = d_in + 1;
end
always # (*)
case(state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S3;
S3: nextstate = S4;
S4: nextstate = S5;
S5: nextstate = S0;
default: nextstate = S0;
endcase
always # (*)
if(state == S0) begin
sel = S0; end
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end
endmodule
At this part
if(state == S0) begin
sel = S0; end
Error (10028): Can't resolve multiple constant drivers for net "sel[4]" at FSM.v(44)
I don't know why this massage come out.
module dec_7seg(
d_in,
seg
);
input [3:0]d_in;
output [7:0]seg;
wire [3:0]d;
assign d[3] = ~ d_in[3];
assign d[2] = ~ d_in[2];
assign d[1] = ~ d_in[1];
assign d[0] = ~ d_in[0];
assign seg[0] = ~(d[3] & d[2] | d[3] & d[1]);
assign seg[1] = ~(~d[2] & d[1] | d[2] & ~d[1] | d[3] & d[0] | d[1] & ~d[0]);
assign seg[2] = ~(d[3] & ~d[2] | d[3] & d[1] | ~d[3] & d[2] & ~d[1] | d[2] &
d[1] & ~d[0] | ~d[2] & ~d[1] & ~d[0]);
assign seg[3] = ~(d[3] & d[2] | d[3] & d[1] | ~d[2] & ~d[0] | d[1] & ~d[0]);
assign seg[4] = ~(d[2] & ~d[1] & d[0] | d[3] & ~d[1] | ~d[2] & d[1] & d[0] |
~d[3] & ~d[2] & ~d[0] | d[2] & d[1] & ~d[0]);
assign seg[5] = ~(~d[3] & d[2] | d[3] & ~d[2] | ~d[1] & d[0] | ~d[2] & ~d[1]
| ~d[2] & d[0]);
assign seg[6] = ~(~d[3] & d[1] & d[0] | d[3] & ~d[1] & d[0] | d[3] & d[1] &
~d[0] | ~d[3] & ~d[1]& ~d[0] | ~d[2] & ~d[1] | ~d[2] & ~d[0]);
assign seg[7] = ~(~d[3] & d[1] | d[2] & d[1] | ~d[2] & ~d[0] | d[3] & ~d[2]
& ~d[1] | ~d[3] & d[2] & d[0]);
endmodule
I want to make it work. But i'm a beginner at verilog.
There are too many problem what i don't know why.
So I want to know the direction to solve that terrible codes...
Your problem is that you are assigned sel here
always # (*)
begin
if(reset) sel = 6'b100_000; // <-- You should assign
// state and d_in here only
else if(count == 10'b11_1111_1111)
state = nextstate;
d_in = d_in + 1;
end
And then assigning sel in another process
always # (*)
if(state == S0) begin
sel = S0; end
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end
endmodule
I think you want it come up in S0 on reset, so you might try this
always # (*)
if(state == S0 || reset) begin // Now you reset sel and assign in
sel = S0; end // the same process
else if(state == S1) begin
sel = S1; end
else if(state == S2) begin
sel = S2; end
else if(state == S3) begin
sel = S3; end
else if(state == S4) begin
sel = S4; end
else begin
sel = S5; end
I'm new to Verilog. Here's what I have done so far and the 4-bit CLA works. However, the 16-bit (using instances of 4-bit CLA) doesn't. The problem is definitely in setting the Cout_itermed (intermediate carries) values from block propagate (BP) and block generate (BG). I've created a module carries to deal with this.
In Xilinx ISE, the output waveform shows up as this (no wave shown):
module CLA_4bit(
output [3:0] S,
output Cout, PG, GG,
input [3:0] A, B,
input Cin
);
wire [3:0] G,P,C;
assign G = A & B; //Generate
assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;
assign PG = P[3] & P[2] & P[1] & P[0]; // block generate
assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]); // block propagate
endmodule
module CLA_16bit(
output reg [15:0] S,
output reg Cout,
input [15:0] A, B,
input Cin
);
reg [3:0] BP, BG;
reg [3:0] Cout_itermed;
carries my_carries(BP, GP, Cin, Cout_itermed, Cout);
CLA_4bit cla0(S[3:0], Cout_itermed[0], BP[0], BG[0], A[3:0], B[3:0], Cin);
CLA_4bit cla1(S[7:4], Cout_itermed[1], BP[1], BG[1], A[7:4], B[7:4], Cout_itermed[0]);
CLA_4bit cla2(S[11:8], Cout_itermed[2], BP[2], BG[2], A[11:8], B[11:8], Cout_itermed[1]);
CLA_4bit cla3(S[15:12], Cout_itermed[3], BP[3], BG[3], A[15:12], B[15:12], Cout_itermed[2]);
Cout = Cout_itermed[3];
endmodule
module carries (
input [3:0] BP,
input [3:0] BG,
input Cin,
output reg [3:0] Cout_itermed,
output reg Cout
);
assign Cout_itermed[0] = BG[0] | (BP[0] & Cin);
assign Cout_itermed[1] = BG[1] | (BP[1] & Cout_itermed[0]);
assign Cout_itermed[2] = BG[2] | (BP[2] & Cout_itermed[1]);
assign Cout = Cout_itermed[3];
endmodule
The waveform does show up (and correctly) when I run a test bench of the 4 bit CLA. Could anyone explain where the problem lies in the carries or the CLA_16bit module?
Cout_itermed has two drivers - the first being the Cout outputs of a CLA_4bit, and the second being the Cout_itermed output of the carries module.
The same applies to Cout in CLA_16bit (though it's two drivers end up being the same signal, Cout_itermed[3], in CLA_16bit and carries).
Remember that in Verilog you're describing physical circuitry, and you should never have two sources (drivers) connected to the same wire - that's how we get short circuits!
The following is based on https://en.wikipedia.org/wiki/Lookahead_carry_unit#16-bit_adder.
What you'll want to do is define remove the Cout_itermed[x] from the Cout port in the CLA_16bits (you can just leave the port hanging). You should move the logic to determine Cout_itermed[3] (i.e. BG[3] | (BP[3]&Cout_itermed[2])) to the carries module.
I have just learned about the CLA adder am a little confused about getting the sum. I see there are two versions of p, p = a or b and p = a xor b.
If I simulate this code it will give the correct result:
module CLA_4bit(
output [3:0] S,
output Cout,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;
assign G = A & B;
assign P = A ^ B;
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;
endmodule
However, if I change P = A ^ B to P = A | B it would give an incorrect sum. What changes to the code would be needed to have it work with P = A | B ?
The formula for S (P^C) is valid for P computed with XOR operation. As you probably know, the only difference in the truth tables between OR and XOR operation is when both bits are 1. That's why the formula for Sshould be slightly different if you use OR operation:
S = (P & (~G)) ^ C
does anybody know what are for PG and GG variables here:
module sum(S, Cout,PG,GG,A,B,Cin);
wire [3:0] G,P,C;
output [3:0] S;
output Cout,PG,GG;
input [3:0] A,B;
input Cin;
assign G = A & B;
assign P = A ^ B;
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S[0] = P[0] ^ C[0];
assign S[1] = P[1] ^ C[1];
assign S[2] = P[2] ^ C[2];
assign S[3] = P[3] ^ C[3];
endmodule
Your code is a four-bit carry-lookahead adder unit. PG and GG can be Group Propagate and Group Generate. PG and GG can be given to another CLA adder unit to combine such units to form a higher bit adder. They are given as
assign PG = P[3] & P[2] & P[1] & P[0];
assign GG = G[3] | P[3] & G[2] | P[3] & P[2] | G[1] | P[3] & P[2] & P[1] & G[0];
More details here. http://en.wikipedia.org/wiki/Lookahead_Carry_Unit#16-bit_adder
GG and PG are output ports which are not driven by the code that you have shown. I can not think of a use for them. Unless they are driven by a hierarchical specifier outside of this module (which is possible, but unusual), their value will always be unknown (x).
Perhaps the original designer had intended to use these outputs, and then forgot to remove them.