I am a beginner in designing circuit using verilog in modelsim. I use a sample code and a tutorial to learn how modelsim works. The code and the testbench are compiled without any problem and even testbench is simulated without any error but the input and output signals are not shown in object windows and they are not under instance menu. please describe for me how can I find them and simulate the waveforms.
here is my code and the test bench.
the definition of a D flipflop
// module D_FF with synchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the
// constructs.
// Concentrate on how the design block is built in a top-down fashion.
always #(negedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
the definition of a T flipflop from D
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule
counter codes:
module rcc4(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule
testbench code:
module stimulus();
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
rcc4 r1(q, clk, reset);
// Control the clk signal that drives the design block. Cycle time = 10
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 200 to 220.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q);
endmodule
I am using modelsim 10.1c on Windows 10.
The following picture is from my project and it shows my object and instance window.
The switch -voptargs=+acc will solve your issue.
vsim -voptargs=+acc modulename
Related
I've been designing a one-shot as part of my EE senior project and am unable to get the 'Reset' to toggle the output to 0.
I used the RTL_viewer in Quartus and the design does match my code: The DFF output (Q) is fed into 2 inverters then into the DFF Reset.
My understanding is that the two inverters should act as buffers. The DFF output should be 0 until the next clock edge is reached. I'm not sure if something is wrong with my design or if this is a timing error. I tried playing around with the clock speed and the buffer delay, but neither produced the correct results.
module oneShot(Clk, Q, Q_bar);
input Clk;
output Q, Q_bar;
logic X, Reset /* synthesis keep */;
logic D = 1'b1;
parameter propogation_delay = 30ns;
not #(propogation_delay) (X, Q);
not #(propogation_delay) (Reset, X);
//instantiation of flip flop
//DFF (Clk, Reset, D, Q);
DFF1 unit0 (Clk, Reset, D, Q);
assign Q_bar = ~ Q;
endmodule
module DFF1 (Clk, Reset, D, Q);
input Clk, Reset, D;
output logic Q;
always_ff #(posedge Clk)
begin
if(Reset == 1'b1)
Q <= 0;
else
Q <= D;
end
endmodule
module oneShot_tb;
logic Clk, Q, Q_bar, Reset;
oneShot DUT (Clk, Q, Q_bar);
always begin
Clk = 0;
#10;
Clk = 1'b1;
#10;
end
initial begin
#300;
$stop;
end
I have written the testbench code and design code for Master-slave JK flip flop, but output isn't coming.
Please point out the error.
Test bench.sv
module JK_ff_tb;
reg clk;
reg reset;
reg j,k;
wire q;
wire qb;
jk_flip_flop_master_slave jkflipflop( .clk(clk), .reset(reset), .j(j), .k(k), .q(q), .q_bar(qb) );
initial begin
$dumpfile("dump.vcd"); $dumpvars;
$monitor(clk,j,k,q,qb,reset);
j = 1'b0;
k = 1'b0;
reset = 1;
clk=1;
#10
reset=0;
j=1'b1;
k=1'b0;
#100
reset=0;
j=1'b0;
k=1'b1;
#100
reset=0;
j=1'b1;
k=1'b1;
#100
reset=0;
j=1'b0;
k=1'b0;
#100
reset=1;
j=1'b1;
k=1'b0;
end
always #25 clk <= ~clk;
endmodule
Design.sv
module jk_flip_flop_master_slave(j,k,clk,reset,q,q_bar);
input j,k,clk,reset;
output q,q_bar;
reg q,q_bar; // Active low reset signal.
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
wire J1;
wire K1;
wire J2; // The actual input to the first SR latch (S).
wire K2; // The actual input to the first SR latch (R).
assign J2 = !reset ? 0 : J1; // Upon reset force J2 = 0
assign K2 = !reset ? 1 : K1; // Upon reset force K2 = 1
and(J1, j, q_bar);
and(K1, k, q);
not(Cn, clk);
sr_latch_gated master(MQ, MQn, clk, J2, K2);
sr_latch_gated slave(q, q_bar, Cn, MQ, MQn);
endmodule // jk_flip_flop_master_slave
Sr_Latched flip flop module
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
I have coded the entire thing in EDA-playground.
The diagram generated was really abrupt as well.
If there is another logic that can be implemented easily, do tell.
I get compile errors on 2 different simulators. You should not declare q and q_bar as reg in the jk_flip_flop_master_slave module. You should delete this line:
reg q,q_bar; // Active low reset signal.
Then it compiles and simulates for me. I see this output:
100xx1
110xx0
010010
110010
010010
110010
101010
001010
101010
001010
...
I'm writing a verilog module for my CompSci class and this module specifically is the data memory module. Structurally and analytically, I'm looking at it and it should work based off of the other files that I have, but I'm not sure why this one specifically is acting up and giving me all x's. Hoping a fresh set of eyes can help find the error I missed. Thanks in advance.
datamem.v:
module datamem(Ina, Inb, enable, readwrite, dataOut, clk, rst);
input wire [31:0] Ina;
input wire [31:0] Inb;
input wire enable;
input wire readwrite;
input wire clk;
input wire rst;
reg [31:0] memory[0:65535];
output reg [31:0] dataOut;
always #(memory[Ina]) begin
dataOut = memory[Ina];
end
always #(posedge clk) begin
if(1'b1 == readwrite) begin
memory[Ina] = Inb;
end
end
endmodule
datamem_tb.v:
module datamem_tb();
reg [31:0] Ina;
reg [31:0] Inb;
reg enable;
reg readwrite;
reg clk;
reg rst;
wire [31:0] dataOut;
datamem DUT (Ina, Inb, enable, readwrite, dataOut, clk, rst);
initial
begin
Ina <= 32'd0;
Inb <= 32'd0;
enable <= 0;
readwrite <= 0;
#20 Ina <= 32'd1234;
#20 Inb <= 32'd1234;
#20 Ina <= 32'd0517;
#20 Inb <= 32'd10259;
end
always #(Ina or Inb)
#1 $display("| Ina = %d | Inb = %d | dataOut = %d |", Ina, Inb, dataOut);
endmodule
A few things as to why you are getting all 'x:
You never run the clock, you need to add something like the following to have the clock toggle:
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
You never assert readwrite which is required to write to your memory module (you set it to 0 on line 20 and never change it). Without being written to, memory will retain its original value of 'x for every element
Aside from that, there are a few other issues with your module:
Use implicit sensitive lists (instead of always #(memory[inA]) use always #(*))
Use non-blocking assignment for your memory write (memory[inA] <= inB)
Consider using $monitor instead of $display for your print statements to avoid timing issues, and you only need call it at the beginning of your initial block in your testbench (http://referencedesigner.com/tutorials/verilog/verilog_09.php)
Your rst and enable arent connected to anything.
Another example of a memory unit implementation can be found here:
Data memory unit
module rff_try_1(q,inp,clk);
input clk,inp;
output q;
reg q;
DFF dff0(q,inp,clk);
endmodule
module DFF(q,inp,clk);
input inp,clk;
output q;
reg q;
always # (posedge clk)begin
if(clk)begin
q=inp;
end
end
endmodule
here I'm using two modules but output is not coming
I'm trying to make two bit right shift register but 1st i have to make one single bit register but even this is not working
There are several mistakes in the code.
1) The line if(clk)begin and relevant end should be removed, posedge clk already describes trigger condition of the flip-flop.
2) A non-blocking assignment (<=) is required for the sequential logic.
The always block should be as follows:
always # (posedge clk) begin
q <= inp;
end
3) Some simulators don't complain, but signal q should be wire in module rff_try_1.
wire q;
Simulation
I simulated the code (after the modifications) on EDA Playground with the testbench below. Used Icarus Verilog 0.9.7 as simulator.
module tb();
reg clk = 1;
always clk = #5 ~clk;
reg inp;
wire q;
rff_try_1 dut(q, inp, clk);
initial begin
inp = 0;
#12;
inp = 1;
#27;
inp = 0;
#24;
inp = 1;
end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#200;
$finish;
end
endmodule
The signal q is as expected as seen on the waveform.
I'm trying to design a 4-bit counter with T-flipflop, here's what i did:
1- From a D-flipflop to T-flipflop:
module T_FlipFlop( clk,T, Q);
input wire clk;
input wire T;
output reg Q;
wire D;
initial
begin
Q<=1'b0;
end
assign D= T ^ Q;
always #(negedge clk)
begin
Q<=D;
end
endmodule
with RTL shematic :
following this "D_ff to T_ff" conversion:
2- Then, i instantiated 4 T-flipflops in the top module and connected the output of each flipflop to the clk of the next one:
module Counters_FreqDividers( sysclk,Q1,Q2,Q3,Q4);
input sysclk;
output wire Q1;
output wire Q2;
output wire Q3;
output wire Q4;
T_FlipFlop num_1(.clk(sysclk),.T(1'b1),.Q(Q1));
T_FlipFlop num_2(.clk(Q1),.T(1'b1),.Q(Q2));
T_FlipFlop num_3(.clk(Q2),.T(1'b1),.Q(Q3));
T_FlipFlop num_4(.clk(Q3),.T(1'b1),.Q(Q4));
endmodule
with RTL schematic :
to follow this diagram:
We know that T-flipflop is just a JK-flipflop with J and K connected to each other and that's what we have here, so consider them as T-flipflops.
3-The simulation:
4- Finally, my questions:
1) why Q1 is the ONLY output that operates properly?
2) Why Q2, Q3, Q4 starts with 1 although i have initialized them as 0?
I can't figure out what's missing, i tried to play around but nothing worked and i'm stuck here!
Edit: my testbench:
module test;
// Inputs
reg sysclk;
// Outputs
wire Q1;
wire Q2;
wire Q3;
wire Q4;
// Instantiate the Unit Under Test (UUT)
Counters_FreqDividers uut (
.sysclk(sysclk),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3),
.Q4(Q4)
);
initial begin
// Initialize Inputs
sysclk <= 1'b1;
#200 $finish();
end
always #5 sysclk=~sysclk;
endmodule